System for analog to digital conversion with improved spurious free dynamic range

Patent metadata

Field	Value
Publication number	US-9325339-B2
Application number	US-201213995211-A
Country	US
Kind code	B2
Filing date	May 1, 2012
Priority date	May 1, 2012
Publication date	Apr 26, 2016
Grant date	Apr 26, 2016

Abstract

Generally, this disclosure describes an apparatus, systems and methods for analog to digital conversion with improved spurious free dynamic range. The system includes a segmented ADC circuit with a plurality of interleaved ADC segments, the segmented ADC circuit configured to generate a digital signal including a channel with an associated channel frequency; a frequency down-converter circuit coupled to the segmented ADC circuit, the frequency down-converter circuit configured to frequency shift the digital signal by a frequency offset; a spur frequency prediction circuit coupled to the frequency down-converter circuit, the spur frequency prediction circuit configured to predict frequencies of spurs generated by the ADC segments, the prediction based on the number of ADC segments and based on the sampling rate of the digital signal; the spur frequency prediction circuit further configured to generate the frequency offset based on the predicted spur frequencies and based on a frequency band of the channel; and a filter circuit coupled to the frequency down-converter circuit, the filter circuit configured to remove one or more of the spurs from the frequency shifted digital signal to generate a filtered signal.

First claim

What is claimed is:

1. An analog to digital conversion (ADC) system comprising:
a segmented ADC circuit comprising a plurality of interleaved ADC segments, said segmented ADC circuit configured to generate a digital signal comprising a channel, said channel associated with a channel frequency;
a frequency down-converter circuit coupled to said segmented ADC circuit, said frequency down-converter circuit configured to frequency shift said digital signal by a frequency offset;
a spur frequency prediction circuit coupled to said frequency down-converter circuit, said spur frequency prediction circuit configured to predict frequencies of spurs generated by said ADC segments, said prediction based on the number of said ADC segments and based on the sampling rate of said digital signal; said spur frequency prediction circuit further configured to generate said frequency offset based on said predicted spur frequencies and based on a frequency band of said channel; and
a filter circuit coupled to said frequency down-converter circuit, said filter circuit configured to remove one or more of said spurs from said frequency shifted digital signal to generate a filtered signal.

2. The ADC system of claim 1 , wherein said predicted spur frequencies are harmonic multiples of said sampling rate of said digital signal divided by said number of ADC segments.

3. The ADC system of claim 1 , wherein said frequency offset is generated by selecting the frequency of said predicted spur frequencies that lies within said channel frequency band.

4. The ADC system of claim 1 , wherein said spur frequency prediction circuit is further configured to generate said frequency offset in response to determining that one of said predicted spur frequencies lies within said channel frequency band.

5. The ADC system of claim 1 , wherein said filter circuit is configured as a DC notch filter.

6. The ADC system of claim 3 , further comprising a frequency shift correction circuit coupled to said filter circuit, said frequency shift correction configured to frequency shift said filtered signal by a second frequency offset, said second frequency offset based on a difference between said selected spur frequency and said channel frequency band.

7. The ADC system of claim 6 , wherein said frequency shift correction circuit further comprises a low pass filter circuit configured to remove one or more remaining harmonics of said spurs.

8. A method for analog to digital conversion, said method comprising:
configuring a plurality of interleaved ADC segments to generate a digital signal comprising a channel, said channel associated with a channel frequency band;
predicting frequencies of spurs generated by said ADC segments, said prediction based on the number of said ADC segments and based on the sampling rate of said digital signal;
in response to determining that one of said predicted spur frequencies lies within said channel frequency band, generating a frequency offset based on said predicted spur frequencies and based on said channel frequency band;
frequency shifting said digital signal by said frequency offset; and
filtering one or more of said spurs from said frequency shifted digital signal.

9. The method of claim 8 , wherein said predicted spur frequencies are harmonic multiples of said sampling rate of said digital signal divided by said number of ADC segments.

10. The method of claim 8 , wherein said frequency offset generation further comprises selecting the frequency of said predicted spur frequencies that lies within said channel frequency band.

11. The method of claim 8 , wherein said filtering further comprises employing a DC notch filter.

12. The method of claim 10 , further comprising frequency shifting said filtered signal by a second frequency offset, said second frequency offset based on a difference between said selected spur frequency and said channel frequency band.

13. The method of claim 11 , further comprising low pass filtering to remove one or more remaining harmonics of said spurs.

14. A non-transitory computer-readable storage medium having instructions stored thereon which when executed by a processor result in the following operations for estimating receiver noise variance, said operations comprising:
configuring a plurality of interleaved ADC segments to generate a digital signal comprising a channel, said channel associated with a channel frequency band;
predicting frequencies of spurs generated by said ADC segments, said prediction based on the number of said ADC segments and based on the sampling rate of said digital signal;
in response to determining that one of said predicted spur frequencies lies within said channel frequency band, generating a frequency offset based on said predicted spur frequencies and based on said channel frequency band;
frequency shifting said digital signal by said frequency offset; and
filtering one or more of said spurs from said frequency shifted digital signal.

15. The computer-readable storage medium of claim 14 , wherein said predicted spur frequencies are harmonic multiples of said sampling rate of said digital signal divided by said number of ADC segments.

16. The computer-readable storage medium of claim 15 , wherein said frequency offset generation further comprises selecting the frequency of said predicted spur frequencies that lies within said channel frequency band.

17. The computer-readable storage medium of claim 15 , wherein said filtering further comprises employing a DC notch filter.

18. The computer-readable storage medium of claim 14 , wherein said operations further comprise frequency shifting said filtered signal by a second frequency offset, said second frequency offset based on a difference between said selected spur frequency and said channel frequency band.

19. The computer-readable storage medium of claim 18 , wherein said operations further comprise low pass filtering to remove one or more remaining harmonics of said spurs.

20. A mobile communication platform comprising:
a processor;
a memory coupled to said processor;
an input/output (I/O) system coupled to said processor;
a display coupled to said I/O system; and
an ADC system coupled to said processor, said ADC system comprising:
a segmented ADC circuit comprising a plurality of interleaved ADC segments, said segmented ADC circuit configured to generate a digital signal comprising a channel, said channel associated with a channel frequency;
a frequency down-converter circuit coupled to said segmented ADC circuit, said frequency down-converter circuit configured to frequency shift said digital signal by a frequency offset;
a spur frequency prediction circuit coupled to said frequency down-converter circuit, said spur frequency prediction circuit configured to predict frequencies of spurs generated by said ADC segments, said prediction based on the number of said ADC segments and based on the sampling rate of said digital signal; said spur frequency prediction circuit further configured to generate said frequency offset based on said predicted spur frequencies and based on a frequency band of said channel; and
a filter circuit coupled to said frequency down-converter circuit, said filter circuit configured to remove one or more of said spurs from said frequency shifted digital signal to generate a filtered signal.

21. The mobile communication platform of claim 20 , wherein said predicted spur frequencies are harmonic multiples of said sampling rate of said digital signal divided by sai

Assignees

• Cowley Nicholas P
• Ali Isaac
• Barber William L
• Intel Corp

Inventors

• Cowley Nicholas P
• Ali Isaac
• Barber William L

Classifications

• H03M1/0626 Primary

  by filtering · CPC title

• H03H7/01

  Frequency selective two-port networks · CPC title

• H03M1/1215

  using time-division multiplexing · CPC title

• H03M1/124 Primary

  Sampling or signal conditioning arrangements specially adapted for A/D converters · CPC title

• H03B28/00

  Generation of oscillations by methods not covered by groups H03B5/00 - H03B27/00, including modification of the waveform to produce sinusoidal oscillations (analogue function generators for performing computing operations G06G7/26; use of transformers for conversion of waveform in AC-AC converters H02M5/18) · CPC title