Systems, methods and media of optimization of temporary read errors in 3D NAND memory devices

Patent metadata

Field	Value
Publication number	US-12136453-B2
Application number	US-202217879593-A
Country	US
Kind code	B2
Filing date	Aug 2, 2022
Priority date	Aug 2, 2022
Publication date	Nov 5, 2024
Grant date	Nov 5, 2024

Abstract

The present disclosure provides systems, methods and media of optimization of temporary read errors (TRE) in three-dimensional (3D) NAND memory devices. The (3D) NAND memory devices comprises a plurality of memory cells arranged as an array of NAND memory strings, a plurality of word lines couple to the memory cells, and a controller. The controller is configured to determine whether a next read operation is a first read operation of the memory device after recovering from an idle state, and in response to a positive result of the determination, control the memory device to perform an extended pre-phase of the first read operation before a read-phase of the first read operation.

First claim

What is claimed is:

1. A memory device, comprising:
a plurality of memory cells arranged as an array of NAND memory strings;
a plurality of word lines coupled to the memory cells; and
a controller configured to:
determine whether a next read operation is a first read operation of the memory device after recovering from an idle state, and
in response to a positive result of the determination, control the memory device to perform an extended pre-phase of the first read operation before a read-phase of the first read operation, wherein the first read operation comprises:
ramping up selected word lines from a ground voltage to a read pass voltage; and
after a first time period, ramping down the selected word lines from the read pass voltage to the ground voltage.

2. The memory device of claim 1 , wherein the extended pre-phase of the first read operation further comprises:
ramping up bottom select gates and top select gates in unselected NAND memory strings from the ground voltage to the read pass voltage; and
after the first time period, ramping down the bottom select gates and top select gates in the unselected NAND memory strings from the read pass voltage to the ground voltage.

3. The memory device of claim 1 , wherein the controller is further configured to:
after the extended pre-phase of the first read operation, control the memory device to perform the read-phase and a post-phase of the first read operation,
wherein a first time duration of the extended pre-phase of the first read operation is least two times a second time duration of the post-phase of the first read operation.

4. The memory device of claim 3 , wherein the post-phase of the first read operation comprises:
ramping up selected word lines from the ground voltage to the read pass voltage; and
after a second time period, ramping down the selected word lines from the read pass voltage to the ground voltage,
wherein the first time period is at least two times the second time period.

5. The memory device of claim 1 , wherein the controller is further configured to:
in response to a negative result of the determination, control the memory device to perform a non-extended pre-phase, a read-phase and a post phase of a non-first read operation,
wherein a first time duration of the extended pre-phase of the first read operation is least two times a third time duration of the non-extended pre-phase of the non-first read operation.

6. The memory device of claim 5 , wherein the non-extended pre-phase of the non-first read operation comprises:
ramping up the selected word lines from the ground voltage to the read pass voltage; and
after a third time period, ramping down the selected word lines from the read pass voltage to the ground voltage,
wherein the first time period is at least two times the third time period.

7. The memory device of claim 1 , wherein the controller is further configured to apply more than one read voltage to the selected word lines during a read phase of the first read operation.

8. A method of performing read operations of a memory device, comprising:
determining whether a next read operation is a first read operation of the memory device after recovering from an idle state; and
in response to a positive result of the determination, performing an extended pre-phase of the first read operation before a read-phase of the first read operation, wherein performing the extended pre-phase of the first read operation comprises:
ramping up selected word lines from a ground voltage to a read pass voltage; and
after a first time period, ramping down the selected word lines from the read pass voltage to the ground voltage.

9. The method of claim 8 , wherein performing the extended pre-phase of the first read operation further comprises:
ramping up bottom select gates and top select gates in unselected NAND memory strings from the ground voltage to the read pass voltage; and
after the first time period, ramping down the bottom select gates and top select gates in the unselected NAND memory strings from the read pass voltage to the ground voltage.

10. The method of claim 8 , further comprising:
after the extended pre-phase of the first read operation, performing the read-phase and a post-phase of the first read operation,
wherein a first time duration of the extended pre-phase of the first read operation is least two times a second time duration of the post-phase of the first read operation.

11. The method of claim 10 , wherein performing the post-phase of the first read operation comprises:
ramping up selected word lines from the ground voltage to the read pass voltage; and
after a second time period, ramping down the selected word lines from the read pass voltage to the ground voltage,
wherein the first time period is at least two times the second time period.

12. The method of claim 11 , further comprising:
in response to a negative result of the determination, performing a non-extended pre-phase, a read-phase and a post phase of a non-first read operation,
wherein a first time duration of the extended pre-phase of the first read operation is least two times a third time duration of the non-extended pre-phase of the non-first read operation.

13. The method of claim 12 , wherein performing the non-extended pre-phase of the non-first read operation comprises:
ramping up the selected word lines from the ground voltage to the read pass voltage; and
after a third time period, ramping down the selected word lines from the read pass voltage to the ground voltage,
wherein the first time period is at least two times the third time period.

14. The method of claim 8 , further comprising applying more than one read voltage to the selected word lines during a read phase of the first read operation.

15. A non-transitory medium having instructions stored thereon that, upon execution by at least one controller, cause the at least one controller to perform a method of performing read operations of a memory device, the method comprising:
determining whether a next read operation is a first read operation of the memory device after recovering from an idle state; and
in response to a positive result of the determination, performing an extended pre-phase of the first read operation before a read-phase of the first read operation, wherein performing the extended pre-phase of the first read operation comprises:
ramping up selected word lines from a ground voltage to a read pass voltage; and
after a first time period, ramping down the selected word lines from the read pass voltage to the ground voltage.

16. The non-transitory medium of claim 15 , wherein performing the extended pre-phase of the first read operation further comprises:
ramping up bottom select gates and top select gates in unselected NAND memory strings from the ground voltage to the read pass voltage; and
after the first time period, ramping down the bottom select gates and top select gates in the unselected NAND memory strings from the read pass voltage to the ground voltage.

17. The non-transitory medium of claim 16 , wherein the method further comprises:
after the extended pre-phase of the first read operation, performing the read-phase and a post-phase of the first read operation,
wherein a first time duration of the extended pre-phase of the first read operation is least two times a second time duration of the post-phase of the first read operation.

18. The non-transitory medium of claim 17 , wherein performing the post-phase of the first read operation comprises:
ramp

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Jia Jianquan
• You Kaikai
• Jia Xinlei
• Zhou Wen
• Yang Kun
• Han Jiayin
• Xu Pan
• Luo Zhe
• Li Da
• Jin Lei

Classifications

• G11C11/4085

  Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge · CPC title

• G11C11/4076

  Timing circuits (for regeneration management G11C11/406) · CPC title

• G11C11/4074

  Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/32

  Timing circuits · CPC title