Method and apparatus for performing on-system phase-locked loop management in memory device

Patent metadata

Field	Value
Publication number	US-11784652-B2
Application number	US-202217878042-A
Country	US
Kind code	B2
Filing date	Jul 31, 2022
Priority date	Jul 23, 2020
Publication date	Oct 10, 2023
Grant date	Oct 10, 2023

Abstract

A method and apparatus for performing on-system phase-locked loop (PLL) management in a memory device are provided. The method may include: utilizing a processing circuit within the memory controller to set multiple control parameters among multiple parameters stored in a register circuit of a transmission interface circuit within the memory controller, for controlling parameter adjustment of a PLL of the transmission interface circuit; utilizing a trimming control circuit to perform the parameter adjustment of the PLL according to the multiple control parameters, to adjust a set of voltage parameters among the multiple parameters, for optimizing a control voltage of a voltage controlled oscillator (VCO); and during the parameter adjustment of the PLL, utilizing the trimming control circuit to generate and store multiple processing results in the register circuit, for being sent back to the processing circuit, to complete the parameter adjustment of the PLL, thereby achieving the on-system PLL management.

First claim

What is claimed is:

1. A method for performing on-system phase-locked loop (PLL) management in a memory device, the method being applied to a memory controller of the memory device, the memory device comprising the memory controller and a non-volatile (NV) memory, the NV memory comprising at least one NV memory element, the method comprising:
utilizing a processing circuit within the memory controller to set multiple control parameters among multiple parameters stored in a register circuit of a transmission interface circuit within the memory controller, for controlling parameter adjustment of a PLL of the transmission interface circuit;
utilizing the transmission interface circuit to perform the parameter adjustment of the PLL according to the multiple control parameters, to adjust a set of voltage parameters among the multiple parameters, for optimizing a control voltage of a voltage controlled oscillator (VCO) in the PLL, wherein the control voltage corresponds to the set of voltage parameters, and an oscillation frequency of the VCO corresponds to the control voltage; and
during the parameter adjustment of the PLL, in response to at least one predetermined condition of the parameter adjustment of the PLL being satisfied, utilizing the transmission interface circuit to generate and store multiple processing results in the register circuit, for being sent back to the processing circuit, to complete the parameter adjustment of the PLL, thereby achieving the on-system PLL management of the memory device;
wherein the memory controller optimizes the control voltage with aid of an optimization working flow regarding the control voltage of the VCO; and operations of the optimization working flow comprise:
determining whether the memory device is in a power-up phase or an adapt equalization phase to generate a first determination result;
in response to the first determination result indicating that the memory device is in the power-up phase or the adapt equalization phase, according to at least one predetermined rule, determining whether the parameter adjustment of the PLL is needed to generate a second determination result;
in response to the second determination result indicating that the parameter adjustment of the PLL is needed, triggering the parameter adjustment of the PLL with a trim-enable parameter among the multiple control parameters;
generating and storing the multiple processing results in the register circuit, for being sent back to the processing circuit, to complete the parameter adjustment of the PLL; and
after completion of the parameter adjustment of the PLL, controlling the memory device to enter an idle state of the memory device and stay in the idle state until any event occurs.

2. The method of claim 1 , wherein the memory controller intermittently performs the parameter adjustment of the PLL and accesses the NV memory in response to one or more host commands of a host device.

3. The method of claim 1 , wherein the any event represents one of multiple predetermined events, and the multiple predetermined events comprise a speed mode change and any host command received from a host device.

4. The method of claim 1 , wherein in a first case that the any event represents a write command from a host device, the memory controller stores data into the NV memory for the host device in response to the write command from the host device, and controls the memory device to enter the idle state again after completing processing corresponding to the write command, wherein the processing corresponding to the write command comprises writing the data into the NV memory.

5. The method of claim 4 , wherein in a second case that the any event represents a read command from the host device, the memory controller reads the stored data from the NV memory in response to the read command from the host device, and provides the host device with said stored data read from the NV memory, and controls the memory device to enter the idle state again after completing processing corresponding to the read command, wherein the processing corresponding to the read command comprises reading the stored data and providing the host device with said stored data.

6. The method of claim 1 , wherein in a second case that the any event represents a read command from a host device, the memory controller reads stored data from the NV memory in response to the read command from the host device, and provides the host device with said stored data read from the NV memory, and controls the memory device to enter the idle state again after completing processing corresponding to the read command, wherein the processing corresponding to the read command comprises reading the stored data and providing the host device with said stored data.

7. A memory device, comprising:
a non-volatile (NV) memory, arranged to store information, wherein the NV memory comprises at least one NV memory element; and
a memory controller, coupled to the NV memory, arranged to control operations of the memory device, wherein the memory controller comprises:
a processing circuit, arranged to control the memory controller according to a plurality of host commands from a host device, to allow the host device to access the NV memory through the memory controller; and
a transmission interface circuit, coupled to the processing circuit, arranged to perform communications with the host device, wherein the transmission interface circuit comprises:
a phase-locked loop (PLL); and
a register circuit, arranged to store multiple parameters of the PLL, and store multiple processing results of parameter adjustment of the PLL, wherein the multiple parameters comprise multiple control parameters;

wherein:
the memory controller utilizes the processing circuit to set the multiple control parameters, for controlling the parameter adjustment of the PLL;
the memory controller utilizes the transmission interface circuit to perform the parameter adjustment of the PLL according to the multiple control parameters, to adjust a set of voltage parameters among the multiple parameters, for optimizing a control voltage of a voltage controlled oscillator (VCO) in the PLL, wherein the control voltage corresponds to the set of voltage parameters, and an oscillation frequency of the VCO corresponds to the control voltage; and
during the parameter adjustment of the PLL, in response to at least one predetermined condition of the parameter adjustment of the PLL being satisfied, the memory controller utilizes the transmission interface circuit to generate and store the multiple processing results in the register circuit, for being sent back to the processing circuit, to complete the parameter adjustment of the PLL, thereby achieving on-system PLL management of the memory device;

wherein the memory controller optimizes the control voltage with aid of an optimization working flow regarding the control voltage of the VCO; and operations of the optimization working flow comprise:
determining whether the memory device is in a power-up phase or an adapt equalization phase to generate a first determination result;
in response to the first determination result indicating that the memory device is in the power-up phase or the adapt equalization phase, according to at least one predetermined rule, determining whether the parameter adjustment of the PLL is needed to generate a second determination result;
in response to the second determination result indicating that the parameter adjustment of the PLL is needed, triggering the parameter adjustment of the PLL with a trim-enable parameter among the multiple control parameters;
generating and storing the multiple processing results in the register circuit, for being sent back to the processing circuit, to complete the param

Assignees

• Silicon Motion Inc

Inventors

• Shih Fu-Jen

Classifications

• H03L7/235 Primary

  Nested phase locked loops · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title

• H03L7/085

  concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00) · CPC title

• H03L7/187

  using means for coarse tuning the voltage controlled oscillator of the loop (H03L7/191 - H03L7/195 take precedence) · CPC title

• G06F13/1668 Primary

  Details of memory controller · CPC title