Integrated circuit and operation method thereof

Patent metadata

Field	Value
Publication number	US-9575535-B2
Application number	US-201414320663-A
Country	US
Kind code	B2
Filing date	Jul 1, 2014
Priority date	Oct 9, 2013
Publication date	Feb 21, 2017
Grant date	Feb 21, 2017

Abstract

An integrated circuit and an operation method thereof are provided. The integrated circuit includes a voltage detecting unit, a central processing unit, a memory unit and a control unit. The voltage detecting unit detects a system voltage and correspondingly outputs a voltage state signal. The central processing unit has at least one register. When the system voltage is downed to a voltage level lower than or equal to a brown-out voltage and greater than a reset low voltage, the control unit stores values of the registers into the memory unit.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a voltage detecting unit configured to detect a system voltage and correspondingly output a voltage state signal;
a central processing unit having at least one register, coupled to the voltage detecting unit for receiving the system voltage, and configured to determine whether to start operating according to the voltage state signal;
a memory unit; and
a control unit coupled to the voltage detecting unit, the central processing unit and the memory unit, and configured to receive the voltage state signal and the system voltage, and when the system voltage is downed to a voltage level lower than or equal to a brown-out voltage and greater than a reset low voltage, the central processing unit entering an idle state and the control unit storing values of the at least one register into the memory unit,
wherein, during the idle state, the control unit reads the values of the at least one register stored in the memory unit and writes the reading values of the at least one register into the at least one register when the system voltage is upped to the voltage level greater than the reset low voltage and lower than or equal to the brown-out voltage.

2. The integrated circuit of claim 1 , wherein the control unit provides a force idle command to the central processing unit to control the central processing unit to enter the idle state when the system voltage is downed to the voltage level lower than or equal to the brown-out voltage and greater than the reset low voltage.

3. The integrated circuit of claim 1 , wherein the control unit provides a power-off command to the central processing unit to control the central processing unit to enter a power-off state when the control unit completely stores the values of the at least one register into the memory unit.

4. The integrated circuit of claim 1 , wherein the central processing unit is switched to enter a reset state when the system voltage is downed to the voltage level lower than or equal to the reset low voltage.

5. The integrated circuit of claim 1 , wherein the control unit sets a resume flag when the control unit completely stores the values of the at least one register into the memory unit, and the control unit resets the resume flag when the control unit completely rewrites the values of the at least one register stored in the memory unit into the at least one register.

6. The integrated circuit of claim 1 , wherein the control unit reads the values of the at least one register stored in the memory unit and writes the values into the at least one register when a pre-read operation is executed by the control unit and the system voltage is upped to the voltage level greater than the reset low voltage and lower than or equal to the brown-out voltage ,and
wherein, the central processing unit starts operating when the system voltage is upped to the voltage level greater than the brown-out voltage.

7. The integrated circuit of claim 1 , wherein a time required for the control unit to read the values of the at least one register and completely store the values of the at least one register into the memory unit is less than or equal to a time for the system voltage to be downed from the brown-out voltage to the reset low voltage.

8. The integrated circuit of claim 1 , wherein a minimum operating voltage of the memory unit is equal to the reset low voltage.

9. The integrated circuit of claim 1 , further comprising:
an access gateway coupled to the central processing unit, the memory unit and the control unit, the control unit turning on the access gateway for the central processing unit to access the memory unit when the system voltage is upped to the voltage level greater than the brown-out voltage, and the control unit cutting off the access gateway when the system voltage is downed to the voltage level lower than and equal to the brown-out voltage.

10. The integrated circuit of claim 1 , further comprising a joint test action group (JTAG) and/or an in-circuit emulator (ICE), wherein the control unit integrates the joint test action group and/or the in-circuit emulator.

11. An operation method of an integrated circuit, comprising:
determining whether a system voltage provided to a central processing unit is downed to or upped to a voltage level greater than a reset low voltage and lower than or equal to a brown-out voltage;
storing a part or all of values of the at least one register of the central processing unit into a memory unit and then entering an idle state when the system voltage is downed to the voltage level lower than or equal to the brown-out voltage and greater than the reset low voltage; and
writing the part or all of the values of the at least one register stored in the memory unit into the at least one register when the system voltage is upped to the voltage level greater than the reset low voltage and lower than or equal to the brown-out voltage.

12. The operation method of the integrated circuit of claim 11 , further comprising:
providing a force idle command to the central processing unit to control the central processing unit to enter the idle state when the system voltage is downed to the voltage level lower than or equal to the brown-out voltage and greater than the reset low voltage.

13. The operation method of the integrated circuit of claim 11 , further comprising:
controlling the central processing unit o enter a power-off state when the values of the at least one register are completely stored into the memory unit.

14. The operation method of the integrated circuit of claim 13 , further comprising:
switching the central processing unit to enter a reset state when the system voltage is downed to the voltage level lower than or equal to the reset low voltage.

15. The operation method of the integrated circuit of claim 11 , further comprising:
setting a resume flag when the control unit completely stores the values of the at least one register into the memory unit; and
resetting the resume flag when the control unit completely rewrites the values of the at least one register stored in the memory unit into the at least one register.

16. The operation method of the integrated circuit of claim 11 , further comprising:
writing the values of the at least one register stored in the memory unit into the at least one register when a pre-read operation being executed and the system voltage is upped to the voltage level greater than the reset low voltage and lower than or equal to the brown-out voltage ; and
starting operating the central processing unit when the system voltage is upped to the voltage level greater than the brown-out voltage.

17. The operation method of the integrated circuit of claim 11 , wherein a time required for reading the values of the at least one register and completely storing the values of the at least one register into the memory unit is less than or equal to a time for the system voltage to be downed from the brown-out voltage to the reset low voltage.

18. The operation method of the integrated circuit of claim 11 , wherein a minimum operating voltage of the memory unit is equal to the reset low voltage.

19. An operation method of an integrated circuit, comprising:
determining whether a central processing unit is in an idle state;
determining whether a system voltage provided to the central processing unit is downed to or upped to a voltage level greater than a reset low voltage and lower than or equal to a brown-out voltage when the central processing unit is in the idle state;

Assignees

• Nuvoton Technology Corp

Inventors

• Wang Cheng-Chih

Classifications

• G06F1/3203

  Power management, i.e. event-based initiation of a power-saving mode · CPC title

• H03K17/24 Primary

  Storing the actual state when the supply voltage fails · CPC title

• G06F1/305 Primary

  in the event of power-supply fluctuations · CPC title