Memory module with local synchronization and method of operation

Patent metadata

Field	Value
Publication number	US-12135644-B2
Application number	US-202218059958-A
Country	US
Kind code	B2
Filing date	Nov 29, 2022
Priority date	Jul 27, 2013
Publication date	Nov 5, 2024
Grant date	Nov 5, 2024

Abstract

A memory module is operable in a computer system having a memory controller and a system bus and comprises memory devices organized in one or more ranks and in a plurality of groups, and circuits configurable to receive from the memory controller a system clock and input control and address (C/A) signals, and output registered C/A signals and buffer control signals. The memory module further comprises a plurality of buffer circuits. In response to the buffer control signals, each buffer circuit is configured to communicate first data/strobe signals with at least one memory device and to communicate second data/strobe signals with the memory controller.
The buffer circuit includes at least one delay circuit configured to delay at least one signal of the first data/strobe signals based on a first delay and a second delay. A respective local clock signal has a respective phase relationship with the module clock signal and is output to a corresponding group of the memory devices that includes at least one corresponding memory device in each of the one or more ranks.

First claim

We claim:

1. A memory module operable in a computer system having a memory controller and a system bus, the system bus including a set of address/control (C/A) signal lines and a plurality of sets of data/strobe signal lines, the memory module comprising:
a printed circuit board (PCB) including connectors along an edge thereof for connecting to the set of C/A signal lines and the plurality of sets of data/strobe signal lines;
a plurality of buffer circuits mounted on the PCB, each buffer circuit of the plurality of buffer circuits corresponding to a respective set of the plurality of sets of data/strobe signal lines and including one or more configuration registers, one or more delay control circuit, and one or more delay circuits, the one or more delay circuits to adjust timing of one or more signals in the each buffer circuit of the plurality of buffer circuits;
a module control circuit mounted on the PCB and configurable to receive from the memory controller input address and control (C/A) signals associated with a read or write operation via the set of C/A signal lines, to output registered C/A signals associated with the read or write operation via first module control signal lines, and to output buffer control signals associated with the memory read or write operation via second module control signal lines;
memory devices mounted on the PCB and organized in ranks, the memory devices including a plurality of groups of memory devices, a respective group of memory devices corresponding to a respective buffer circuit of the plurality of buffer circuits and including at least one respective memory device in each of the ranks;
wherein:
in response to the registered C/A signals, at least one first memory device in a first group of the plurality of groups of memory devices is configured to receive or output first data/strobe signals;
in response to the buffer control signals, a first buffer circuit of the plurality of buffer circuits is configured to output or receive the first data/strobe signals and to receive or output second data/strobe signals, the second data/strobe signals corresponding, respectively, to the first data/strobe signals and being communicated between the memory module and the memory controller via a first set of data/strobe signal lines of the plurality of sets of data/strobe signal lines;
at least one delay circuit of the one or more delay circuits in the first buffer circuit is configured to delay at least one signal in the first buffer circuit based on a first delay and a second delay, each of the at least one signal being related to a corresponding signal in the first data/strobe signals or the second data/strobe signals;
the memory module is operable in a configuration mode, and the first delay is programed into and stored in at least one configuration register of the one or more configuration registers in the first buffer circuit in response to mode register command signals received from the memory controller via the set of C/A signal lines during the configuration mode; and
the second delay is determined by at least one delay control circuit of the one or more delay control circuits in the first buffer circuit while the memory module is not operating in the configuration mode.

2. The memory module of claim 1 , wherein the at least one configuration register provides static control of the timing of the at least one signal and the at least one delay control circuit provides dynamic control of the timing of the at least one signal.

3. The memory module of claim 1 , wherein
the buffer control signals include one or more mode signals indicating a read or write operation and one or more signals carrying information for controlling data paths in the plurality of buffer circuits; and
in the configuration mode, the module control circuit is configured to output configuration control signals to the buffer circuits in response to the mode register command signals, the configuration control signals including one or more mode signals indicating the configuration mode and one or more signals carrying configuration information for programming the one or more configuration registers.

4. The memory module of claim 3 , wherein the each buffer circuit further includes logic configured to program the one or more configuration registers in response to the configuration information.

5. The memory module of claim 1 , wherein the at least one signal includes at least one data signal and/or at least one strobe signal received from the at least one first memory device in the first group of memory devices.

6. The memory module of claim 1 , wherein the at least one delay control circuit in the first buffer circuit is configured to determine the second delay based on at least one signal received from the module control circuit and at least one signal received from the memory controller during a memory operation.

7. The memory module of claim 1 , wherein:
the system bus further includes one or more clock signal lines;
the module control circuit is further configurable to receive from the memory controller a system clock via the one or more clock signal lines and output a registered clock; and
the first buffer circuit is configured to receive the registered clock and to generate a first buffered clock, the first buffered clock having a programmable phase relationship with the registered clock determined by at least one of the one or more registers in the first buffer circuit.

8. The memory module of claim 7 , wherein the first buffer circuit is further configured to output the first buffered clock to the first group of memory devices.

9. The memory module of claim 1 , wherein the memory module is configurable to perform a set of training operations including at least one write operation to write a set of data into a set of memory locations on the memory module and at least one read operation to read from the set of memory locations; and
wherein at least one of the one or more configuration registers is programmed based on information derived from the set of training operations.

10. The memory module of claim 1 , wherein the at least one delay circuit in the first buffer circuit is configured to delay the at least one signal based on a combination of the first delay and the second delay.

11. A method performed at a memory module in a computer system, the computer system having a memory controller and a system bus, the system bus including a set of address/control (C/A) signal lines and a plurality of sets of data/strobe signal lines, the memory module comprising a printed circuit board (PCB) including connectors along an edge thereof for connecting to the set of C/A signal lines and the plurality of sets of data/strobe signal lines, and memory devices mounted on the PCB and organized in ranks, the method comprising:
operating in a configuration mode, including:
receiving mode register command signals from the memory controller via the C/A signal lines; and
programing one or more configuration registers in each buffer circuit of a plurality of buffer circuits in response to the mode register command signals, wherein the plurality of buffer circuits are mounted on the PCB and each buffer circuit of the plurality of buffer circuits corresponds to a respective set of the plurality of sets of data/strobe signal lines, wherein the memory devices include a plurality of groups of memory devices, each group of the plurality of groups of memory devices corresponding to a respective buffer circuit of the plurality of buffer circuits and including at least one respective memory device in each of the ranks; and

performing a memory read or write operation, including:
receiving from the memory controller i

Assignees

• Netlist Inc

Inventors

• Lee Hyun
• Bhakta Jayesh R

Classifications

• G11C7/1093

  Input synchronization · CPC title

• G11C7/1066

  Output synchronization · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title

• G11C29/023

  in clock generator or timing circuitry · CPC title

• G11C5/04 Primary

  Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports · CPC title