Latency adjustment based on stack position identifier in memory devices configured for stacked arrangements

Patent metadata

Field	Value
Publication number	US-9153298-B2
Application number	US-201213534279-A
Country	US
Kind code	B2
Filing date	Jun 27, 2012
Priority date	Dec 13, 2011
Publication date	Oct 6, 2015
Grant date	Oct 6, 2015

Abstract

Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, ReRAMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM is adjusted based on the SPID of that device. In another embodiment, a latency of a DRAM or SRAM is adjusted based on the SPID. In another embodiment, internal regulation signals are shared with other devices via TSVs. In another embodiment, adjustments to internally regulated signals are made based on the SPID of a particular device. In another embodiment, serially connected signals can be controlled based on a chip SPID (e.g., an even or odd stack position), and whether the signal is an upstream or a downstream type of signal.

First claim

What is claimed is:

1. A semiconductor memory device, comprising:
a stack position identifier configured to identify a position of the semiconductor memory device in an aligned vertical stack of a plurality of semiconductor memory devices, wherein the plurality of semiconductor devices are coupled together via a common vertical connection;
a latency determiner configured to determine a programmed latency from a mode register on the semiconductor memory device; and
a latency ad…

Assignees

• Stephens Jr Michael C
• Iii Holdings 2 Llc

Inventors

• Stephens Jr Michael C

Classifications

• H10W90/722

  Electricity · mapped topic

• G11C2029/4402

  Physics · mapped topic

• G11C7/22

  Physics · mapped topic

• G11C16/30

  Physics · mapped topic

• G11C5/04

  Physics · mapped topic