Electronic shelf label and method for assembling the same

US12131670B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12131670-B2
Application numberUS-202016971190-A
CountryUS
Kind codeB2
Filing dateFeb 12, 2020
Priority dateFeb 19, 2019
Publication dateOct 29, 2024
Grant dateOct 29, 2024

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An electronic shelf label and a method for assembling the same. The electronic shelf label including: a housing, the housing including a front housing and a rear housing, the front housing and the rear housing being coupled with each other, a chamber being provided between the front housing and the rear housing, the rear housing including an opening; a motherboard, the motherboard being located in the chamber; a back plate, the back plate covering the opening, the motherboard being detachably coupled to the back plate, the back plate being detachably coupled to the rear housing, and an orthographic projection of the back plate in a plane where the rear housing is located being located in the rear housing.

First claim

Opening claim text (preview).

The invention claimed is: 1. An electronic shelf label, comprising: a housing, the housing comprising a front housing and a rear housing, the front housing and the rear housing being coupled with each other, a chamber being provided between the front housing and the rear housing, the rear housing comprising an opening; a motherboard, the motherboard being located in the chamber; a back plate, the back plate covering the opening, the motherboard being detachably coupled to the back plate, the back plate being detachably coupled to the rear housing; a circuit board, wherein the circuit board is located on a side of the motherboard facing towards the back plate, and the circuit board is fixed to the motherboard, wherein the motherboard comprises a communication interface, the back plate has a convex portion, the convex portion has a cavity for accommodating the communication interface. 2. The electronic shelf label according to claim 1 , wherein the back plate together with the motherboard is detachably coupled to the rear housing. 3. The electronic shelf label according to claim 2 , wherein the motherboard is configured to pass through the opening of the rear housing to reach the chamber. 4. The electronic shelf label according to claim 1 , wherein the motherboard is configured to pass through the opening of the rear housing to reach the chamber. 5. The electronic shelf label according to claim 4 , wherein the motherboard and the rear housing are located on a same side of the back plate, an area of the opening is larger than an area of the motherboard, so that the motherboard passes through the opening of the rear housing. 6. The electronic shelf label according to claim 1 , wherein a gap is provided between the motherboard and the back plate, a height of the gap is greater than or equal to a height of the circuit board. 7. The electronic shelf label according to claim 1 , wherein the communication interface comprises a power interface, the power interface is located on a surface of the motherboard facing towards the back plate, the convex portion comprises a first convex portion at a position corresponding to the power interface, the first convex portion covers the power interface. 8. The electronic shelf label according to claim 7 , wherein the first convex portion comprises a first via hole, an end of the power interface and the first via hole are connected with each other, an end of the first convex portion away from the back plate is flush with an end of the power interface away from the motherboard. 9. The electronic shelf label according to claim 8 , wherein the communication interface further comprises a network interface, the network interface is located on the surface of the motherboard facing towards the back plate, the back plate is provided with a second convex portion at a position corresponding to the network interface, the second convex portion covers the network interface. 10. The electronic shelf label according to claim 7 , wherein the communication interface further comprises a network interface, the network interface is located on the surface of the motherboard facing towards the back plate, the convex portion further comprises a second convex portion at a position corresponding to the network interface, the second convex portion covers the network interface. 11. The electronic shelf label according to claim 10 , wherein the second convex portion comprises a second via hole, an end of the network interface and the second via hole are connected with each other, an end of the second convex portion away from the back plate is flush with an end of the network interface away from the motherboard. 12. The electronic shelf label according to claim 11 , wherein the network interface and the power interface are located on a same surface of the motherboard, and the network interface and the power interface are adjacent to each other, the second convex portion and the first convex portion are coupled to each other. 13. The electronic shelf label according to claim 12 , wherein the second convex portion, the first convex portion, and the back plate are formed as an integral structure. 14. The electronic shelf label according to claim 12 , wherein the motherboard is detachably coupled to the back plate by a first fastener, and the back plate is detachably coupled to the rear housing by a second fastener, the first fastener is closer to the circuit board than the second fastener. 15. A method for assembling an electronic shelf label, the electronic shelf label comprising: a housing, the housing comprising a front housing and a rear housing, the front housing and the rear housing being coupled with each other, a chamber being provided between the front housing and the rear housing, the rear housing comprising an opening; a motherboard, the motherboard being located in the chamber; a back plate, the back plate covering the opening, the motherboard being detachably coupled to the back plate, the back plate being detachably coupled to the rear housing; and a circuit board, wherein the circuit board is located on a side of the motherboard facing towards the back plate, and the circuit board is fixed to the motherboard; wherein the motherboard comprises a communication interface, the back plate has a convex portion, the convex portion has a cavity for accommodating the communication interface, wherein the method comprising: coupling the front housing with the rear housing to form the chamber; fixing the motherboard to the back plate; and fixing the back plate to the rear housing, wherein at a same time of fixing the back plate to the rear housing, the motherboard passes through the opening of the rear housing and reaches the chamber.

Assignees

Inventors

Classifications

  • G09F3/208Primary

    Electronic labels, Labels integrating electronic displays · CPC title

  • G09F3/204Primary

    specially adapted to be attached to a shelf or the like · CPC title

  • Adjacent components · CPC title

  • Non-printed connector · CPC title

  • having connector relating features for connecting the connector pins with the PCB or for mounting the connector body with the housing · CPC title

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What does patent US12131670B2 cover?
An electronic shelf label and a method for assembling the same. The electronic shelf label including: a housing, the housing including a front housing and a rear housing, the front housing and the rear housing being coupled with each other, a chamber being provided between the front housing and the rear housing, the rear housing including an opening; a motherboard, the motherboard being located…
Who is the assignee on this patent?
Boe Technology Group Co Ltd
What technology area does this patent fall under?
Primary CPC classification G09F3/208. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Oct 29 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).