Multi-mode sigma-delta ADC circuit and microphone circuit having a multi-mode sigma-delta ADC circuit

Patent metadata

Field	Value
Publication number	US-12126366-B2
Application number	US-202217950486-A
Country	US
Kind code	B2
Filing date	Sep 22, 2022
Priority date	Sep 22, 2022
Publication date	Oct 22, 2024
Grant date	Oct 22, 2024

Abstract

Embodiments of multi-mode sigma-delta analog-to-digital converter (ADC) circuits and a microphone circuit are disclosed. In an embodiment, a multi-mode sigma-delta ADC circuit includes a pair of operational transconductance amplifiers (OTAs), a filter connected to the pair of OTAs, a quantizer connected to the filter, a differential digital-to-analog converter (DAC) connected to the quantizer, and a controller configured to switch the multi-mode sigma-delta ADC circuit between a single-ended operational mode, a pseudo differential operational mode, and a full differential operational mode to improve common mode rejection (CMR) performance by controlling the pair of OTAs. An output of a microphone and a differential output of the differential DAC are inputted into input terminals of the pair of OTAs.

First claim

What is claimed is:

1. A multi-mode sigma-delta analog-to-digital converter (ADC) circuit, the multi-mode sigma-delta ADC circuit comprising:
a pair of operational transconductance amplifiers (OTAs);
a filter connected to the pair of OTAs;
a quantizer connected to the filter;
a differential digital-to-analog converter (DAC) connected to the quantizer, wherein an output of a microphone and a differential output of the differential DAC are inputted into a plurality of input terminals of the pair of OTAs; and
a controller configured to switch the multi-mode sigma-delta ADC circuit between a single-ended operational mode, a pseudo differential operational mode, and a full differential operational mode to improve common mode rejection (CMR) performance by controlling the pair of OTAs.

2. The multi-mode sigma-delta ADC circuit of claim 1 , wherein the microphone is a single-ended microphone.

3. The multi-mode sigma-delta ADC circuit of claim 2 , wherein the controller is further configured to operate the multi-mode sigma-delta ADC circuit under the single-ended operational mode.

4. The multi-mode sigma-delta ADC circuit of claim 3 , wherein the controller is further configured to disable a first OTA of the pair of OTAs and to enable a second OTA of the pair of OTAs.

5. The multi-mode sigma-delta ADC circuit of claim 2 , wherein the controller is further configured to operate the multi-mode sigma-delta ADC circuit under the pseudo differential operational mode.

6. The multi-mode sigma-delta ADC circuit of claim 5 , wherein the controller is further configured to enable each OTA of the pair of OTAs.

7. The multi-mode sigma-delta ADC circuit of claim 6 , wherein a component of the differential output of the differential DAC is constant.

8. The multi-mode sigma-delta ADC circuit of claim 7 , wherein the component of the differential output of the differential DAC is equal to an input voltage to the multi-mode sigma-delta ADC circuit.

9. The multi-mode sigma-delta ADC circuit of claim 1 , wherein the microphone is a differential microphone.

10. The multi-mode sigma-delta ADC circuit of claim 9 , wherein the controller is further configured to operate the multi-mode sigma-delta ADC circuit under the full differential operational mode.

11. The multi-mode sigma-delta ADC circuit of claim 1 , wherein the quantizer comprises a one-bit quantizer and a digital integrator connected to the one-bit quantizer.

12. The multi-mode sigma-delta ADC circuit of claim 11 , wherein the one-bit quantizer and the digital integrator are operated under a same clock signal.

13. A multi-mode sigma-delta analog-to-digital converter (ADC) circuit, the multi-mode sigma-delta ADC circuit comprising:
a pair of operational transconductance amplifiers (OTAs);
a filter connected to the pair of OTAs;
a quantizer connected to the filter;
a differential digital-to-analog converter (DAC) connected to the quantizer, wherein the DAC comprises a plurality of resistors and a plurality of switches connected to the resistors, wherein an output of a microphone and a differential output of the differential DAC are inputted into a plurality of input terminals of the pair of OTAs; and
a controller configured to switch the multi-mode sigma-delta ADC circuit between a single-ended operational mode, a pseudo differential operational mode, and a full differential operational mode to improve common mode rejection (CMR) performance by controlling the pair of OTAs.

14. The multi-mode sigma-delta ADC circuit of claim 13 , wherein the microphone is a single-ended microphone.

15. The multi-mode sigma-delta ADC circuit of claim 14 , wherein the controller is further configured to disable a first OTA of the pair of OTAs and to enable a second OTA of the pair of OTAs under the single-ended operational mode.

16. The multi-mode sigma-delta ADC circuit of claim 13 , wherein the controller is further configured to enable each OTA of the pair of OTAs under the pseudo differential operational mode.

17. The multi-mode sigma-delta ADC circuit of claim 16 , wherein a component of the differential output of the differential DAC is constant under the pseudo differential operational mode.

18. The multi-mode sigma-delta ADC circuit of claim 13 , wherein the microphone is a differential microphone, and wherein the controller is further configured to operate the multi-mode sigma-delta ADC circuit under the full differential operational mode.

19. The multi-mode sigma-delta ADC circuit of claim 13 , wherein the quantizer comprises a one-bit quantizer and a digital integrator connected to the one-bit quantizer.

20. A microphone circuit, the microphone circuit comprising:
a microphone; and
a multi-mode sigma-delta analog-to-digital converter (ADC) circuit connected to the microphone, the multi-mode sigma-delta ADC circuit comprising:
a pair of operational transconductance amplifiers (OTAs);
a filter connected to the pair of OTAs;
a quantizer connected to the filter;
a differential digital-to-analog converter (DAC) connected to the quantizer, wherein an output of the microphone and a differential output of the differential DAC are inputted into a plurality of input terminals of the pair of OTAs; and
a controller configured to switch the multi-mode sigma-delta ADC circuit between a single-ended operational mode, a pseudo differential operational mode, and a full differential operational mode to improve common mode rejection (CMR) performance by controlling the pair of OTAs.

Assignees

• Nxp Bv

Inventors

• Kroekenstoel Dave Sebastiaan
• Kamran Muhammad
• Neuteboom Harry
• Ligouras Costantino
• Rueda Gómez Sergio Andrés

Classifications

• H03M3/354

  at one point, i.e. by adjusting a single reference value, e.g. bias or gain error · CPC title

• H03M1/12

  Analogue/digital converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H04R3/00

  Circuits for transducers (arrangements for producing a reverberation or echo sound G10K15/08; amplifiers H03F) · CPC title

• H03M3/392

  Arrangements for selecting among plural operation modes, e.g. for multi-standard operation · CPC title

• H03M3/484 Primary

  by adapting the gain of the feedback signal, e.g. by adapting the reference values of the digital/analogue converter in the feedback path · CPC title