Multi-level sigma-delta ADC with reduced quantization levels

Patent metadata

Field	Value
Publication number	US-8963755-B2
Application number	US-201214351111-A
Country	US
Kind code	B2
Filing date	Oct 10, 2012
Priority date	Oct 13, 2011
Publication date	Feb 24, 2015
Grant date	Feb 24, 2015

Abstract

A multi-level sigma-delta Analog to Digital converter provides multi-level outputs using a quantizer with reduced quantization levels. The converter comprises a direct path comprising a computation block, an analog integrator, a digital integrator and the quantizer with reduced quantization levels. Further, the converter comprises a feedback path arranged to provide to the computation block a feedback analog signal. The feedback analog signal is injected via the feedback path and the computation block directly at the input terminal of the quantizer. The converter allows reduction of the complexity of the quantizer.

First claim

The invention claimed is:

1. A multi-level sigma-delta Analog-to-Digital converter comprising:
a direct path having an input terminal to receive an input analog signal and an output terminal to provide an output digital signal corresponding to said input analog signal, said direct path comprising:
an analog integrator having an input terminal to receive a first analog signal representative of the input analog signal and an output terminal to provide a second analog signal,
a first computation block arranged to receive said second analog signal and to provide a first analog computed signal;
a quantizer having a respective input terminal connected to the first computation block to receive the first analog computed signal and a respective output terminal operatively connected to the output terminal of the direct path,

wherein said direct path of the converter further comprises a digital integrator interposed between the output terminal of the quantizer and the output terminal of the converter, said digital integrator comprising a delay block having an input terminal to receive the output digital signal and an output terminal to provide a delayed digital signal,
wherein said direct path further comprises a second computation block arranged to receive a third analog signal representative of the input analog signal and to provide a second analog computed signal,
the converter further comprising a first feedback path arranged to provide to the first computation block a feedback analog signal representative of the delayed digital signal present at the output terminal of the delay block of the digital integrator, said first computation block being arranged to subtract said feedback analog signal from the second analog signal, the converter being characterized in that said feedback analog signal is injected via the first feedback path and the first computation block directly at the input terminal of the quantizer,
the converter further comprising a second feedback path, wherein the second feedback path comprises a digital-to-analog converter having an input connected to the output terminal of the direct path and an output connected to second computation block, said input is used to receive the output digital signal present at the output terminal of the direct path.

2. The converter of claim 1 , wherein the second feedback path is arranged to provide to the second computation block a further feedback analog signal representative of the output digital signal present at the output terminal of the direct path, said second computation block being arranged to subtract said further feedback analog signal to the third analog signal.

3. The converter of claim 1 , wherein the direct path further comprises a first amplification block interposed between the second computation block and the first computation block.

4. The converter of claim 3 , wherein the first amplification block is interposed between second computation block and the analog integrator.

5. The converter of claim 3 , wherein the first amplification block is interposed between the analog integrator and the first computation block.

6. The converter of claim 1 , wherein the direct path further comprises a further analog integrator having an input terminal operatively connected to the input terminal of the direct path and an output terminal operatively connected to the second computation block to provide it the third analog signal representative of the input analog signal.

7. The converter of claim 6 , wherein the direct path further comprises a third computation block arranged to receive the input analog signal and to provide a third analog computed signal to the further analog integrator.

8. The converter of claim 7 , wherein the second feedback path is further arranged to provide the further feedback analog signal to the third computation block, said third computation block being arranged to subtract the further feedback analog signal from the input digital signal.

9. The converter of claim 8 , wherein the direct path further comprises a second amplification block interposed between the third computation block and the second computation block.

10. The converter of claim 9 , wherein the second amplification block is interposed between the third computation block and the further analog integrator.

11. The converter of claim 9 , wherein the second amplification block is interposed between the further analog integrator and the second computation block.

12. The converter of claim 7 , wherein the first computation block, the second computation block and the third computation block are configured to change from positive to negative the sign of the feedback analog signals received from the feedback paths.

13. The converter of claim 1 , wherein the first feedback path further comprises a digital-to-analog converter interposed between the output terminal of the delay block of the digital integrator and the first computation block.

14. A digital audio device comprises the converter of claim 1 .

Assignees

• St Ericsson Sa

Inventors

• Pinna Carlo

Classifications

• H03M3/454

  with distributed feedback, i.e. with feedback paths from the quantiser output to more than one filter stage · CPC title

• H03M3/424

  the quantiser being a multiple bit one · CPC title

• H03M3/30 Primary

  Delta-sigma modulation · CPC title

• H03M3/39 Primary

  Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators (of digital delta-sigma modulators H03M7/3004) · CPC title