Sigma-delta analog-to-digital converter

Patent metadata

Field	Value
Publication number	US-11962331-B2
Application number	US-202217814978-A
Country	US
Kind code	B2
Filing date	Jul 26, 2022
Priority date	Aug 6, 2021
Publication date	Apr 16, 2024
Grant date	Apr 16, 2024

Abstract

A sigma-delta ADC is described including a passive filter with an input coupled to the ADC input and a filter output. A gain stage has an input connected to the filter output. A quantiser has an input connected to the gain stage output and a quantiser output. The passive filter includes a first filter resistor between the filter input and the filter output and a filter capacitor having first terminal coupled to the filter output. A feedback resistor is coupled between the quantiser output and the filter output and receives a negative of the value of the output to provide negative feedback to the filter output. The gain stage has a capacitor and resistor in series, and a gain element connected to the gain stage input and an output connected to the gain stage output. One terminal of the gain stage capacitor is connected to the gain element output.

First claim

The invention claimed is:

1. A sigma-delta analog to digital converter (ADC) comprising:
an input;
an output;
a passive filter having a filter output, and a filter input coupled to the input;
a gain stage having a gain stage output, and a gain stage input coupled to the filter output;
a quantiser having a quantiser input coupled to the gain stage output, and a quantiser output coupled to the output; and
a feedback resistor having a feedback resistor first terminal coupled to the filter output, and a feedback resistor second terminal configured to receive a negative of a value of the output; and

wherein
the passive filter comprises a first filter resistor coupled between the filter input and the filter output, and a filter capacitor having a filter capacitor second terminal, and a filter capacitor first terminal coupled to the filter output;
the gain stage comprises: a gain element having a gain element input coupled to the gain stage input, and a gain element output coupled to the gain stage output; a first gain stage capacitor having a first gain stage capacitor first terminal coupled to the gain element output; and a first gain stage resistor having a first gain stage resistor first terminal coupled to a first gain stage capacitor second terminal and a first gain stage resistor second terminal; and wherein the gain element comprises one of a transconductance amplifier and a series arrangement of an operational amplifier and a second gain stage resistor.

2. The sigma-delta ADC of claim 1 wherein the gain stage further comprises:
a chopper circuit having a chopper circuit first input coupled to the passive filter output, a chopper circuit second input coupled to ground, a chopper circuit first output coupled to the gain element input, and a chopper circuit second output coupled to a gain element further input; and
a de-chopper circuit having a de-chopper circuit first input coupled to the gain element output, a de-chopper circuit second input coupled to a gain element further output, a de-chopper circuit first output coupled to the quantiser input, and a second de-chopper output coupled to a quantiser further input.

3. The sigma-delta ADC of claim 1 comprising an inverting circuit for providing the negative of a value of the output, the inverting circuit having an inverting circuit input coupled to the output, and an inverting circuit output coupled to the feedback resistor first terminal.

4. The sigma-delta ADC of claim 1 wherein the quantiser comprises a clocked comparator.

5. The sigma-delta ADC of claim 1 further comprising a counter having a counter input coupled to the quantiser output, and a counter output, wherein the counter is configured to vary the counter output dependent on the quantiser output value.

6. The sigma-delta ADC of claim 5 further comprising:
one or more further feedback resistors in parallel with the feedback resistor, each of the one or more further feedback resistors having a first terminal coupled to the passive filter output; and
a plurality of switches arranged in parallel and configured to switchably couple one of a first voltage and a second voltage to a respective one of the feedback resistor second terminal and the one or more further feedback resistor second terminals dependent on the counter output.

7. The sigma-delta ADC of claim 6 further comprising a dynamic element matching circuit, arranged between the counter output and the plurality of switches, and configured to control the plurality of switches dependent on the counter output value.

8. The sigma-delta ADC of claim 5 wherein the passive filter further comprises a second filter resistor, having a second filter resistor first terminal coupled to the filter capacitor second terminal and a second filter resistor second terminal coupled to ground, and wherein the first gain stage resistor second terminal is coupled to ground.

9. The sigma-delta ADC of claim 1 wherein the filter capacitor second terminal and the first gain stage resistor second terminal are coupled to ground.

10. The sigma-delta ADC of claim 1 further comprising:
a further input;
a further output;
wherein the passive filter has a filter further input coupled to the further input, and a filter further output coupled to the filter capacitor second terminal;
the gain stage has a gain stage further output, and a gain stage further input coupled to the filter further output;
the quantiser has a further quantiser input coupled to the gain stage further output, and a quantiser further output coupled to the further output; wherein
the passive filter comprises a second filter resistor having a second filter resistor first terminal coupled to the filter further input and a second filter resistor second terminal coupled to the filter further output;
the gain element has a gain element further input coupled to the gain stage further input, and a gain element further output coupled to the gain stage further output, and the gain stage further comprises a second gain stage capacitor coupled between the gain element further output and the first gain stage resistor second terminal; and
the sigma-delta ADC further comprises a further feedback resistor having a further feedback resistor first terminal coupled to the output and a further feedback resistor first terminal coupled to the passive filter further output; and wherein the feedback resistor first terminal is coupled to the further output and the feedback resistor second terminal is coupled to the passive filter output.

11. The sigma-delta ADC of claim 10 wherein the gain stage further comprises:
a chopper circuit having a chopper circuit first input coupled to the passive filter output, a chopper circuit second input coupled to the filter further output, a chopper circuit output coupled to the gain element input, and a chopper circuit second output coupled to the gain element further input; and
a de-chopper circuit having a de-chopper first input coupled to the gain element output, a de-chopper second input coupled to the gain element further output, a de-chopper first output coupled to the gain stage output, and a de-chopper second output coupled to the gain stage further output.

12. The sigma-delta ADC of claim 10 or 11 wherein the quantiser comprises a clocked comparator.

13. The sigma-delta ADC of claim 10 further comprising a counter having a counter input coupled to the quantiser output, and a counter output, and configured to vary the counter output dependent on the quantiser output value; and a further counter having a further counter input coupled to the quantiser further output, and a further counter output, and configured to vary the further counter output dependent on the further quantiser output.

14. The sigma-delta ADC of claim 13 further comprising:
one or more first further feedback resistors arranged in parallel with the feedback resistor, each of the feedback resistor and one or more first further feedback resistors having a first terminal coupled to the filter output; and a plurality of switches configured to switchably couple one of a first voltage and a second voltage to a respective second terminal of the feedback resistor and the one or more first further feedback resistors dependent on the counter output value; and
one or more second further feedback resistors arranged in parallel with the further feedback resistor, each of the further feedback resistor and the one or more second further feedback resistors having a first terminal coupled to the filter further output; and a plurality of further switches configured to switchably couple one of the first voltage and the second vo

Assignees

• Nxp Bv

Inventors

• Van Veldhoven Robert

Classifications

• H03M3/434 Primary

  with multi-level feedback · CPC title

• H03M3/456

  the modulator having a first order loop filter in the feedforward path · CPC title

• H03M3/49

  in feedback mode, i.e. by determining the range to be selected from one or more previous digital output values · CPC title

• H03M3/494 Primary

  Sampling or signal conditioning arrangements specially adapted for delta-sigma type analogue/digital conversion systems · CPC title

• H03M3/464

  Details of the digital/analogue conversion in the feedback path · CPC title