Methods and apparatus for voltage buffering

Patent metadata

Field	Value
Publication number	US-12126309-B2
Application number	US-201916557571-A
Country	US
Kind code	B2
Filing date	Aug 30, 2019
Priority date	Aug 31, 2018
Publication date	Oct 22, 2024
Grant date	Oct 22, 2024

Abstract

In an example apparatus, a first transistor has a base terminal, a first current terminal and a second current terminal. The base terminal is coupled to an input voltage node. A second transistor has a control terminal, a third current terminal and a fourth current terminal. The third current terminal is coupled to the second current terminal. The fourth current terminal is coupled to a first resistor. A second resistor is coupled to the control terminal. An inductor is coupled between the first resistor and a ground terminal.

First claim

What is claimed is:

1. An apparatus, comprising:
a voltage follower circuit having a voltage follower input, a power terminal, and a voltage follower output, the voltage follower circuit including a first transistor coupled between the power terminal and the voltage follower output, the first transistor including a bipolar junction transistor BJT) and having a first control terminal coupled to the voltage follower input;
an inductor having first and second inductor terminals, the first inductor terminal coupled to a ground terminal; and
a current source coupled between the voltage follower output and the second inductor terminal, the current source including a second transistor, the second transistor including a field effect transistor (FET) and having a second control terminal coupled to a bias input.

2. The apparatus of claim 1 , wherein the voltage follower input is a first voltage follower input, the voltage follower output is a first voltage follower output, the current source is a first current source, the inductor is a first inductor, and the apparatus further comprises:
a second voltage follower circuit having a second voltage follower input, the power terminal, and a second voltage follower output, the second voltage follower circuit including a third transistor coupled between the power terminal and the second voltage follower output, the third transistor having a third control terminal coupled to the second voltage follower input;
a second inductor having third and fourth inductor terminals, the third inductor terminal coupled to the ground terminal; and
a second current source coupled between the second voltage follower output and the fourth inductor terminal, the second current source including a fourth transistor having a fourth control terminal coupled to the bias input.

3. The apparatus of claim 2 , further comprising: a first resistor coupled between the bias input and the second control terminal, and a second resistor coupled between the bias input and the fourth control terminal.

4. The apparatus of claim 1 , further comprising a resistor coupled between the bias input and the second control terminal.

5. An apparatus, comprising:
a voltage follower circuit having a voltage follower input, a power terminal, and a voltage follower output, the voltage follower circuit including a first transistor coupled between the power terminal and the voltage follower output, the first transistor including a bipolar junction transistor (BJT) and having a first control terminal coupled to the voltage follower input;
a current source coupled between the voltage follower output and a ground terminal, the current source including a second transistor, the second transistor including a field effect transistor (FET) and having a second control terminal; and
a resistor coupled between a bias input and the second control terminal.

6. The apparatus of claim 5 , wherein the resistor is a first resistor, and the apparatus further includes a second resistor having first and second resistor terminals, the first resistor terminal coupled to the power terminal, and the first transistor coupled between the second resistor terminal and the voltage follower output.

7. The apparatus of claim 5 , wherein a first impedance of the resistor is higher than a second impedance of the second control terminal.

8. The apparatus of claim 5 , further comprising an inductor having first and second inductor terminals, the first inductor terminal coupled to the ground terminal, and the second transistor coupled between the second inductor terminal and the voltage follower output.

9. The apparatus of claim 5 , wherein the resistor is a first resistor, the voltage follower input is a first voltage follower input, the voltage follower output is a first voltage follower output, the current source is a first current source, and the apparatus further comprises:
a second voltage follower circuit having a second voltage follower input, the power terminal, and a second voltage follower output, the second voltage follower circuit including a third transistor coupled between the power terminal and the second voltage follower output, the third transistor having a third control terminal coupled to the second voltage follower input;
a second current source coupled between the second voltage follower output and the ground terminal, the second current source including a fourth transistor having a fourth control terminal; and
a second resistor coupled between the bias input and the fourth control terminal.

10. The apparatus of claim 9 , further comprising a second inductor having third and fourth inductor terminals, the third inductor terminal coupled to the ground terminal, and the fourth transistor coupled between the second voltage follower output and the fourth inductor terminal.

11. The apparatus of claim 9 , wherein the first and second voltage follower inputs are differential inputs, and the first and second voltage follower outputs are differential outputs.

12. An apparatus, comprising:
a first voltage follower circuit having a first voltage follower input, a power terminal, and a first voltage follower output, the first voltage follower circuit including a first transistor coupled between the power terminal and the first voltage follower output, the first transistor including a bipolar junction transistor (BJT) and having a first control terminal coupled to the first voltage follower input;
a first current source coupled between the first voltage follower output and a ground terminal, the first current source including a second transistor, the second transistor including a field effect transistor (FET) and having a second control terminal;
a second voltage follower circuit having a second voltage follower input, the power terminal, and a second voltage follower output, the second voltage follower circuit including a third transistor coupled between the power terminal and the second voltage follower output, the third transistor including a BJT and having a third control terminal coupled to the second voltage follower input;
a second current source coupled between the second voltage follower output and the ground terminal, the second current source including a fourth transistor, the fourth transistor including a FET and having a fourth control terminal;
a first resistor coupled between a bias input and the second control terminal; and
a second resistor coupled between the bias input and the fourth control terminal.

13. The apparatus of claim 12 , wherein the first and third transistors include respective N-type BJTs, and the second and fourth transistors include respective NFETs.

14. The apparatus of claim 12 , further comprising:
a first inductor having first and second inductor terminals, in which the first inductor terminal is coupled to the ground terminal, and the second transistor is coupled between the first voltage follower output and the second inductor terminal; and
a second inductor having third and fourth inductor terminals, in which the third inductor terminal is coupled to the ground terminal, and the fourth transistor is coupled between the second voltage follower output and the fourth inductor terminal.

15. The apparatus of claim 12 , further comprising a third resistor having first and second resistor terminals, the first resistor terminal coupled to the power terminal, the first transistor coupled between the second resistor terminal and the first voltage follower output, and the third transistor coupled between the second resistor terminal and the second voltage follower output.

16. The apparatus of claim

Assignees

• Texas Instruments Inc

Inventors

• Akhtar Siraj
• Sankaran Swaminathan

Classifications

• H03F1/306

  in junction-FET amplifiers (H03F1/303, H03F1/305, H03F1/309 take precedence) · CPC title

• H03F3/505

  with field-effect devices · CPC title

• H03F3/183

  with semiconductor devices only · CPC title

• H03F2200/03

  the amplifier being designed for audio applications · CPC title

• H03F2200/318

  A matching circuit being used as coupling element between two amplifying stages · CPC title