High linearity push-pull common-gate amplifier

Patent metadata

Field	Value
Publication number	US-9537457-B2
Application number	US-201514629793-A
Country	US
Kind code	B2
Filing date	Feb 24, 2015
Priority date	Feb 24, 2015
Publication date	Jan 3, 2017
Grant date	Jan 3, 2017

Abstract

An amplifier operates to provide a high output impedance at an output through a push stage having a first transistor of a first transistor type and a pull stage having a second transistor of a second transistor type that is different from the first transistor type. The first transistor and the second transistor are coupled in a common-gate configuration. The first transistor and the second transistor are shorted together via a capacitor coupled to an input and share a common current path as a push-pull current-reusing common-gate low noise amplifier with a broadband input matching.

First claim

What is claimed is:

1. An amplifier comprising:
an input terminal configured to receive an input signal;
an output terminal configured to drive an output signal;
a first transistor comprising a first input contact coupled to the input terminal and a first output contact coupled to the output terminal;
a second transistor including a second input contact coupled to the input terminal and a second output contact coupled to the first output contact of the first transistor and the output terminal;
a current bias component, coupled to the first input contact of the first transistor, configured to provide a bias current to the first transistor and the second transistor along a same current path;
a capacitor component, coupled between the first input contact of the first transistor and the second input contact of the second transistor, configured to short the input signal between the first input contact and the second input contact at an operating frequency range and provide the input signal to the first input contact and the second input contact; and
a feedback path coupled between the output terminal and a first control contact of the first transistor or coupled between the output terminal and a second control contact of the second transistor, wherein the feedback path is configured to control a first bias to the first transistor or a second bias to the second transistor based on a reference voltage.

2. The amplifier of claim 1 , further comprising:
an inductor component coupled to the input terminal and configured to provide a DC path for the bias current.

3. The amplifier of claim 1 , wherein the current bias component comprises a third transistor, an integrated resistor or an integrated inductor configured as a current source to provide the bias current to the first transistor and the second transistor along the same current path.

4. The amplifier of claim 1 , wherein the output terminal is coupled at an output node located between the first output contact and the second output contact with a voltage potential between a first supply level and a second supply level that is different from the first supply level.

5. The amplifier of claim 1 , wherein the feedback path comprises a common-mode feedback amplifier comprising:
a first input coupled to the output terminal;
a second input coupled to the reference voltage; and
an output coupled to the first control contact or the second control contact, wherein the first control contact and the second control contact comprise gate contacts of the first transistor and the second transistor, respectively.

6. The amplifier of claim 1 , wherein the first transistor and the second transistor are configured to both amplify the input signal and reuse a current along the same current path.

7. The amplifier of claim 1 , wherein the first input contact and the second input contact comprise source contacts of the first transistor and the second transistor, and the first output contact and the second output contact comprise drain contacts, and wherein the first transistor and the second transistor comprise FET transistors of different PMOS and NMOS transistor types respectively.

8. The amplifier of claim 1 , wherein the first transistor and the second transistor are coupled together in a common gate configuration as a current-reusing common-gate low-noise amplifier configured to vary an input impedance.

9. A communication system comprising:
an input component configured to receive or transmit one or more input signals comprising:
a baseband processor integrated on a single substrate configured to process the one or more input signals;
an amplifier arranged in a common-gate configuration and configured to match an input impedance of the one or more input signals, the amplifier comprising:
an amplifier input terminal configured to receive the one or more input signals;
an amplifier output terminal configured to provide an output signal having a gain based on the one or more input signals;
a push stage comprising a first transistor of a first transistor type coupled to a current supply via a current path;
a pull stage comprising a second transistor of a second transistor type coupled to the push stage and to the current supply via the current path;
a capacitor component, coupled between input contacts of the first transistor and the second transistor, configured to provide the one or more input signals at an operating frequency range to the push stage and the pull stage; and
a feedback path coupled between the amplifier output terminal and a first gate contact of the first transistor or a second gate contact of the second transistor, wherein the feedback path is configured to control a first bias to the first transistor or a second bias to the second transistor based on a reference voltage.

10. The communication system of claim 9 , wherein the first transistor comprises:
a first source contact coupled, via the capacitor component, to the amplifier input terminal and a second source contact of the second transistor; and
a first drain contact coupled, via an output node, to a second drain contact of the second transistor;
wherein the amplifier is configured to provide the output signal at the amplifier output terminal via the output node with the gain that is based on a sum of a transconductance of the first transistor and the second transistor independent of a current consumption of the amplifier.

11. The communication system of claim 9 , wherein the pull stage and the push stage are coupled to one another in a parallel configuration and configured to detect the one or more input signals concurrently.

12. The communication system of claim 9 , wherein the amplifier is located externally to the single substrate.

13. The communication system of claim 9 , wherein the feedback path comprises a common-mode feedback (CMFB) amplifier coupled to the amplifier output terminal at a first CMFB input, a reference voltage at a second CMFB input and a gate contact of the first transistor or the second transistor at a CMFB output.

14. The communication system of claim 13 , wherein the CMFB amplifier is configured to generate a bias level of the output signal that is approximately at a middle level between a first supply level and a second supply level that is different from the first supply level.

15. The communication system of claim 9 , wherein the first gate contact of the first transistor receives a different voltage bias than the second gate contact of the second transistor.

16. The communication system of claim 9 , further comprises an inductor coupled to the amplifier input terminal configured to bias the received one or more input signals.

17. A mobile communication device comprising:
a transceiver component comprising at least one differential amplifier, comprising:
a differential input having a p-input and an n-input;
a differential output having an n-output and a p-output; and
a first amplifier arranged between the p-input and the n-output and a second amplifier arranged between the n-input and the p-output, wherein the first amplifier and the second amplifier are in a common-gate configuration and respectively comprise:
an amplifier input connected to the p-input or to the n-input;
a push stage comprising a first transistor of a PMOS type that is coupled to a current bias;
a pull stage comprising a second transistor of an NMOS type coupled in parallel to the push stage in a common gate configuration and to a current supply via a same current input path as the first transistor; and
a capacitor component including at least one

Assignees

• Intel Ip Corp

Inventors

• Issakov Vadim
• Hirsch Konrad
• Stockinger Herbert
• Doppke Harald

Classifications

• H03F2200/294

  the amplifier being a low noise amplifier [LNA] · CPC title

• H03F1/0233

  by using a signal derived from the output signal, e.g. bootstrapping the voltage supply · CPC title

• H03F2203/30063

  A differential amplifier being used in the bias circuit or in the control circuit of the SEPP-amplifier · CPC title

• H03F1/0216

  Continuous control · CPC title

• H03F3/265 Primary

  with field-effect transistors only · CPC title