Adjustment of a starting voltage corresponding to a program operation in a memory sub-system

Patent metadata

Field	Value
Publication number	US-12125539-B2
Application number	US-202217861467-A
Country	US
Kind code	B2
Filing date	Jul 11, 2022
Priority date	May 28, 2020
Publication date	Oct 22, 2024
Grant date	Oct 22, 2024

Abstract

A processing device determines a measured bit error count (BEC) value corresponding to a read sample offset operation executed on a first programming voltage distribution of memory cells of a plurality of programming voltage distributions of a memory sub-system. The measured BEC value of the portion of the programming voltage distribution is compared to a threshold BEC value to generate a comparison result. In view of the comparison result, an adjusted program start voltage level is determined by adjusting a default program voltage level of a programming process. The programming process including a series of programming pulses is executed, where the adjusted program start voltage level is set as a starting voltage level of a first programming pulse of the series of programming pulses.

First claim

What is claimed is:

1. A method comprising:
determining a measured width value corresponding to a read sample offset operation executed on a first programming voltage distribution of memory cells of a plurality of programming voltage distributions of a memory sub-system;
comparing the measured width value of the first programming voltage distribution to a threshold width value to generate a comparison result;
in view of the comparison result, determining an adjusted program start voltage level by adjusting a default program voltage level of a programming process; and
executing the programming process comprising a series of programming pulses, wherein the adjusted program start voltage level is set as a starting voltage level of a first programming pulse of the series of programming pulses.

2. The method of claim 1 , further comprising:
determining the comparison result indicates satisfaction of a condition wherein the measured width value is less than the threshold width value; and
increasing an initial program voltage level by a voltage step value to determine the adjusted program start voltage level that is set as the starting voltage level.

3. The method of claim 1 , further comprising:
determining the comparison result indicates satisfaction of a condition wherein the measured width value is greater than the threshold width value; and
decreasing an initial program voltage level by a voltage step value to determine the adjusted program start voltage level that is set as the starting voltage level.

4. The method of claim 1 , wherein the read sample offset operation comprises a left offset probe, a center offset probe, a right offset probe, and an additional offset probe.

5. The method of claim 4 , wherein the measured width value corresponds to a read level threshold of the additional offset probe.

6. The method of claim 4 , wherein the measured width value corresponds to a read level threshold of the left offset probe.

7. The method of claim 1 , wherein the programming process comprises an incremental step pulse programming process.

8. A system comprising:
a memory device; and
a processing device, operatively coupled with the memory device, to perform operations comprising:
determining a measured width value corresponding to a read sample offset operation executed on a first programming voltage distribution of memory cells of a plurality of programming voltage distributions of a memory sub-system;
comparing the measured width value of the first programming voltage distribution to a threshold width value to generate a comparison result;
in view of the comparison result, determining an adjusted program start voltage level by adjusting a default program voltage level of a programming process; and
executing the programming process comprising a series of programming pulses, wherein the adjusted program start voltage level is set as a starting voltage level of a first programming pulse of the series of programming pulses.

9. The system of claim 8 , the operations further comprising:
determining the comparison result indicates satisfaction of a condition wherein the measured width value is less than the threshold width value; and
increasing an initial program voltage level by a voltage step value to determine the adjusted program start voltage level.

10. The system of claim 8 , the operations further comprising:
determining the comparison result indicates satisfaction of a condition wherein the measured width value is greater than the threshold width value; and
decreasing an initial program voltage level by a voltage step value to determine the adjusted program start voltage level.

11. The system of claim 8 , wherein the read sample offset operation comprises a left offset probe, a center offset probe, a right offset probe, and an additional offset probe.

12. The system of claim 11 , wherein the measured width value corresponds to a read level threshold of the additional offset probe.

13. The system of claim 8 , wherein the programming process comprises an incremental step pulse programming process.

14. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising:
determining a measured width value corresponding to a read sample offset operation executed on a first programming voltage distribution of memory cells of a plurality of programming voltage distributions of a memory sub-system;
comparing the measured width value of the first programming voltage distribution to a threshold width value to generate a comparison result;
in view of the comparison result, determining an adjusted program start voltage level by adjusting a default program voltage level of a programming process; and
executing the programming process comprising a series of programming pulses, wherein the adjusted program start voltage level is set as a starting voltage level of a first programming pulse of the series of programming pulses.

15. The non-transitory computer-readable storage medium of claim 14 , the operations further comprising:
determining the comparison result indicates satisfaction of a condition wherein the measured width value is less than the threshold width value; and
increasing an initial program voltage level by a voltage step value to determine the adjusted program start voltage level that is set as the starting voltage level.

16. The non-transitory computer-readable storage medium of claim 14 , the operation further comprising:
determining the comparison result indicates satisfaction of a condition wherein the measured width value is greater than the threshold width value; and
decreasing an initial program voltage level by a voltage step value to determine the adjusted program start voltage level that is set as the starting voltage level.

17. The non-transitory computer-readable storage medium of claim 14 , wherein the read sample offset operation comprises a left offset probe, a center offset probe, a right offset probe, and an additional offset probe.

18. The non-transitory computer-readable storage medium of claim 17 , wherein the measured width value corresponds to a read level threshold of the additional offset probe.

19. The non-transitory computer-readable storage medium of claim 17 , wherein the programming process comprises an incremental step pulse programming process.

20. The non-transitory computer-readable storage medium of claim 17 , wherein the measured width value corresponds to a read level threshold of the left offset probe.

Assignees

• Micron Technology Inc

Inventors

• Liikanen Bruce A
• Sheperek Michael
• Koudele Larry J

Classifications

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G11C11/5628

  Programming or writing circuits; Data input circuits · CPC title