Semiconductor device and operating method thereof

Patent metadata

Field	Value
Publication number	US-2016293271-A1
Application number	US-201514953194-A
Country	US
Kind code	A1
Filing date	Nov 27, 2015
Priority date	Mar 31, 2015
Publication date	Oct 6, 2016
Grant date	—

Abstract

A method of operating a semiconductor memory device includes applying a program pulse at least once to each of a plurality of pages; performing a pre-read operation on a reference page among the plurality of pages through an initial test voltage; repeating the pre-read operation by controlling the initial test voltage until a result of the pre-read operation is a pass; setting the initial test voltage of when the result of the pre-read operation is the pass as a reference test voltage; and detecting a defective page among the plurality of pages by performing read operations on the plurality of pages through the reference test voltage.

First claim

What is claimed is:

1 . A method of operating a semiconductor memory device, the method comprising:
applying a program pulse at least once to each of a plurality of pages; performing a pre-read operation on a reference page among the plurality of pages through an initial test voltage; repeating the pre-read operation by controlling the initial test voltage until a result of the pre-read operation is a pass; setting the initial test voltage of when the result of the pre-read operation is the pass as a reference test voltage; and detecting a defective page among the plurality of pages by performing read operations on the plurality of pages through the reference test voltage.

2 . The method of claim 1 , wherein the result of the pre-read operation is determined as the pass when a number of fail bits among data bits read from the reference page through the pre-read operation is less than a critical value.

3 . The method of claim 2 , wherein a data bit having a first logic value among the data bits is defined as a fail bit, and a data bit having a second logic value among the data bits is defined as a pass bit.

4 . The method of claim 3 ,
wherein the repeating of the pre-read operation includes decreasing the initial test voltage, and wherein a data bit of a memory cell having a lower threshold voltage than the initial test voltage in the reference page is determined to have the first logic value, and a data bit of a memory cell having a threshold voltage greater than or equal to the initial test voltage in the reference page is determined to have the second logic value.

5 . The method of claim 3 ,
wherein the repeating of the pre-read operation includes increasing the initial test voltage, and wherein a data bit of a memory cell having a threshold voltage greater than or equal to the initial test voltage in the reference page is determined to have the first logic value, and a data bit of a memory cell having a lower threshold voltage than the initial test voltage in the reference page is determined to have the second logic value.

6 . The method of claim 1 , wherein the detecting of the defective page comprises:
detecting first and second page data by performing read operations on the first and second pages, respectively, among the plurality of pages; generating a first comparative page by performing an OR operation on data bits of the first and second page data; and generating a first error value according to a number of fail bits of the first comparative page.

7 . The method of claim 6 , wherein the detecting of the defective page further comprises:
detecting third page data by performing a read operation on a third page among the plurality of pages; generating a second comparative page by performing an OR operation on the data bits of the second and third page data; generating a second error value according to a number of fail bits of the second comparative page; and detecting the third page as the defective page by comparing the second error value with the first error value.

8 . The method of claim 1 , wherein the detecting of the defective page comprises:
detecting first page data by performing a read operation on a first page among the plurality of pages; counting a number of fall bits of the first page data as a first error value; detecting second page data by performing a read operation on a second page among the plurality of pages; counting a number of fall bits of the second page data as a second error value; and detecting the second page as the defective page by comparing the second error value with the first error value.

9 . The method of claim 1 , wherein the detecting of the defective page comprises:
detecting page data by performing a read operation on each page; and detecting a corresponding page as the defective page when a number of fail bits of the page data is greater than a reference value.

10 . The method of claim 1 , wherein a memory block including the defective page is processed as a bad region.

11 . The method of claim 1 , wherein the defective page is processed as a bad region.

12 . A semiconductor memory device, comprising:
a memory cell array including a plurality of memory blocks, each of which includes a plurality of pages; and a peripheral circuit suitable for performing a pre-read operation on a reference page among the plurality of pages through an Initial test voltage, wherein the peripheral circuit repeats the pre-read operation by controlling the initial test voltage until a result of the pre-read operation is a pass, and wherein the peripheral circuit further sets the initial test voltage of when the result of the pre-read operation is the pass as a reference test voltage, and detects a defective page among the plurality of pages by performing read operations on the plurality of pages through the reference test voltage.

13 . The semiconductor memory device of claim 12 ,
wherein the result of the pre-read operation is determined as the pass when a number of fail bits among data bits read from the reference page through the pre-read operation is less than a critical value.

14 . The semiconductor memory device of claim 12 ,
wherein the peripheral circuit detects the defective page by: detecting first and second page data by performing read operations on the first and second pages, respectively, among the plurality of pages, generating a first comparative page by performing an OR operation on data bits of the first and second page data, generating a first error value according to a number of fall bits of the first comparative page, detecting third page data by performing a read operation on a third page among the plurality of pages, generating a second comparative page by performing an OR operation on the data bits of the second and third page data, generating a second error value according to a number of fail bits of the second comparative page, and detecting the third page data as the defective page by comparing the second error value with the first error value.

15 . The semiconductor memory device of claim 12 , wherein the peripheral circuit further replaces a bad region, which is a memory block having the detected defective page, with a redundancy memory block among the plurality of memory blocks.

16 . A method of operating a semiconductor memory device including a plurality of pages coupled to a plurality of pages, the method comprising:
performing a program operation on each of the plurality of pages by using an incremental step pulse program (ISPP) method using a determined verify voltage; providing an additional program pulse at least once to the plurality of pages through a plurality of word lines; and detecting a defective page from the plurality of pages by performing read operations on the plurality of pages through a reference test voltage greater than the verify voltage by an amount of a determined voltage.

17 . The method of claim 16 ,
wherein the plurality of pages are stacked over the substrate, and wherein each of the plurality of pages is coupled to a corresponding word line located at a predetermined height from the substrate.

18 . The method of claim 16 , wherein the detecting of the defective page comprises:
detecting first and second page data by performing read operations on first and second pages, respectively, among the plurality of pages; generating a first comparative page by performing an OR operation on data bits of the first and second page data; and generating a first error value according to a

Assignees

• Sk Hynix Inc

Inventors

• Won Sam Kyu
• Kim Myung Su
• Cha Jae Won

Classifications

• G11C16/3459

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title

• G11C16/12

  Programming voltage switching circuits · CPC title

• G11C16/28

  using differential sensing or reference cells, e.g. dummy cells · CPC title

• G11C29/04 Primary

  Detection or location of defective memory elements {, e.g. cell constructio details, timing of test signals} · CPC title

• G11C2029/1202

  Word line control · CPC title