Data Storage System and Method for Decoding Data based on Extrapolated Flipped-Bit Data

Patent metadata

Field	Value
Publication number	US-2020117536-A1
Application number	US-201916716378-A
Country	US
Kind code	A1
Filing date	Dec 16, 2019
Priority date	Mar 12, 2013
Publication date	Apr 16, 2020
Grant date	—

Abstract

An error management system for a data storage device can generate soft-decision log-likelihood ratios (LLRs) using multiple reads of memory locations. 0-to-1 and 1-to-0 bit flip count data provided by multiple reads of reference memory locations can be used to generate probability data that is used to generate possible LLR values for decoding target pages. Possible LLR values are stored in one or more look-up tables.

First claim

What is claimed is:

1 . A method for a data storage system, the method comprising:
performing a plurality of reads to generate a plurality of read bit streams, wherein each of the plurality of reads is performed at a respective voltage read level; for each of the plurality of read bit streams, determining flipped-bit data, based on a respective read bit stream and a reference bit stream, wherein the flipped-bit data is different from likelihood ratios (LLRs); extrapolating flipped-bit data based on the determined flipped-bit data for the plurality of read bit streams; generating reference LLR values based on the determined flipped-bit data for the plurality of read bit streams and the extrapolated flipped-bit data, wherein the reference LLR values are different from the extrapolated flipped-bit data; and decoding data using the reference LLR values.

2 . The method of claim 1 , further comprising: determining the reference bit stream from a reference memory location.

3 . The method of claim 1 , wherein the determining flipped-bit data comprises comparing the respective read bit stream and the reference bit stream.

4 . The method of claim 2 , wherein the reference LLR values are associated with the reference memory location.

5 . The method of claim 2 , further comprising: prior to the decoding, storing the reference LLR values, wherein the reference memory location is within the data storage system, and wherein the decoding data comprises decoding the data stored in the data storage system using the stored reference LLR values.

6 . The method of claim 1 , further comprising:
performing a plurality of reads of a target memory location to generate a target read bit stream; generating a sequence of LLR values for decoding the target memory location based at least in part on the reference LLR values and on the target read bit stream; and decoding target data from the target memory location using the generated sequence of LLR values.

7 . The method of claim 6 , further comprising determining the reference bit stream from a reference memory location, wherein the reference memory location and the target memory location are located in a same memory block of a non-volatile memory of the data storage system.

8 . The method of claim 6 , further comprising determining the reference bit stream from a reference memory location, wherein read or write cycling characteristics of the reference memory location and the target memory location are substantially same.

9 . A data storage system, comprising:
a non-volatile memory; and a controller configured to cause:
performing a plurality of reads to generate a plurality of read bit streams, wherein each of the plurality of reads is performed at a respective voltage read level;
for each of the plurality of read bit streams, determining flipped-bit data, based on a respective read bit stream and a reference bit stream, wherein the flipped-bit data is different from likelihood ratios (LLRs);
extrapolating flipped-bit data based on the determined flipped-bit data for the plurality of read bit streams;
generating reference LLR values based on the determined flipped-bit data for the plurality of read bit streams and the extrapolated flipped-bit data, wherein the reference LLR values are different from the extrapolated flipped-bit data; and
decoding data using the reference LLR values.

10 . The data storage system of claim 9 , wherein the controller is configured to cause determining the reference bit stream from a reference memory location.

11 . The data storage system of claim 9 , wherein the determining flipped-bit data comprises comparing the respective read bit stream and the reference bit stream.

12 . The data storage system of claim 10 , wherein the reference LLR values are associated with the reference memory location.

13 . The data storage system of claim 10 , wherein the controller is configured to cause, prior to the decoding, storing the reference LLR values, wherein the reference memory location is within the non-volatile memory, and wherein the decoding data comprises decoding the data stored in the non-volatile memory using the stored reference LLR values.

14 . The data storage system of claim 9 , wherein the controller is configured to cause:
performing a plurality of reads of a target memory location to generate a target read bit stream; generating a sequence of LLR values for decoding the target memory location based at least in part on the reference LLR values and on the target read bit stream; and decoding target data from the target memory location using the generated sequence of LLR values.

15 . The data storage system of claim 14 , wherein the controller is configured to cause: determining the reference bit stream from a reference memory location, and wherein the reference memory location and the target memory location are located in a same memory block of a non-volatile memory of the data storage system.

16 . The data storage system of claim 14 , wherein the controller is configured to cause: determining the reference bit stream from a reference memory location, and wherein read or write cycling characteristics of the reference memory location and the target memory location are substantially same.

17 . A data storage system, comprising:
means for performing a plurality of reads to generate a plurality of read bit streams, wherein each of the plurality of reads is performed at a respective voltage read level; means for determining flipped-bit data for each of the plurality of read bit streams, based on a respective read bit stream and a reference bit stream, wherein the flipped-bit data is different from likelihood ratios (LLRs); means for extrapolating flipped-bit data based on the determined flipped-bit data for the plurality of read bit streams; means for generating reference LLR values based on the determined flipped-bit data for the plurality of read bit streams and the extrapolated flipped-bit data, wherein the reference LLR values are different from the extrapolated flipped-bit data; and means for decoding data using the reference LLR values.

18 . The data storage system of claim 17 , further comprising:
means for performing a plurality of reads of a target memory location to generate a target read bit stream; means for generating a sequence of LLR values for decoding the target memory location based at least in part on the reference LLR values and on the target read bit stream; and means for decoding target data from the target memory location using the generated sequence of LLR values.

19 . The data storage system of claim 17 , further comprising: means for determining the reference bit stream from a reference memory location.

20 . The data storage system of claim 19 , wherein the means for determining flipped-bit data comprises means for comparing the respective read bit stream and the reference bit stream, and wherein the reference LLR values are associated with the reference memory location.

Assignees

• Western Digital Tech Inc

Inventors

• Lu Guangming

Classifications

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G06F11/1048 Primary

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• H03M13/3784

  for soft-output decoding of block codes · CPC title