Integrated power device with energy harvesting gate driver

Patent metadata

Field	Value
Publication number	US-12119739-B2
Application number	US-202217853746-A
Country	US
Kind code	B2
Filing date	Jun 29, 2022
Priority date	Jul 1, 2021
Publication date	Oct 15, 2024
Grant date	Oct 15, 2024

Abstract

An electronic circuit is disclosed. The electronic circuit includes a transistor having a gate terminal, a source terminal and a drain terminal, and a gate driver circuit including a pull-down transistor coupled to the gate terminal, and an input terminal arranged to receive an input signal and generate a corresponding output signal at an output terminal coupled to the gate terminal, where the gate driver circuit is arranged to store energy harvested from the input signal and use the stored energy to change a conductive state of the pull-down transistor. In one aspect, the transistor includes gallium nitride (GaN). In another aspect, the pull-down transistor includes GaN.

First claim

What is claimed is:

1. An electronic circuit comprising:
a transistor including a gate terminal, a source terminal and a drain terminal; and
a gate driver circuit including:
a pull-down transistor coupled to the gate terminal;
an input terminal arranged to receive an input signal and generate a corresponding output signal at an output terminal coupled to the gate terminal;
a pull-up transistor, wherein the input terminal is coupled to a collector terminal of the pull-up transistor; and
wherein the gate driver circuit is arranged to store energy harvested from the input signal through the pull-up transistor and use the stored energy to change a conductive state of the pull-down transistor.

2. The electronic circuit of claim 1 , wherein the transistor comprises gallium nitride (GaN).

3. The electronic circuit of claim 2 , wherein the pull-down transistor comprises GaN.

4. The electronic circuit of claim 1 , wherein the gate driver circuit comprises silicon.

5. The electronic circuit of claim 1 , wherein the gate driver circuit uses the stored energy to transition the pull-down transistor from an on state to an off state.

6. The electronic circuit of claim 1 , wherein the gate driver circuit and the transistor are disposed within a unitary electronic package.

7. The electronic circuit of claim 1 , wherein the input signal is a pulse width modulated (PWM) signal comprising a series of on and off commands.

8. The electronic circuit of claim 7 , wherein the gate driver circuit is arranged to change the conductive state of the pull-down transistor from an off state to an on state during an off command of the PWM signal.

9. The electronic circuit of claim 6 , wherein the unitary electronic package comprises a first, a second and a third external contact.

10. The electronic circuit of claim 1 , wherein the transistor and the gate driver circuit are disposed within a TO-247 package.

11. The electronic circuit of claim 6 , wherein the unitary electronic package is a TO-leadless (TOLL) package.

12. The electronic circuit of claim 7 , wherein the gate driver circuit comprises an energy harvesting circuit coupled to the gate terminal, and wherein the energy harvesting circuit is arranged to store energy harvested from the input signal and use the stored energy for operation of the gate driver circuit when the PWM signal is in an off command.

13. The electronic circuit of claim 9 , wherein the first external contact is a power input contact, the second external contact is a power output contact, and the third external contact is an input signal contact.

Assignees

• Navitas Semiconductor Ltd

Inventors

• Giandalia Marco
• Zhang Jason
• Jia Hongwei
• Kinzer Daniel M

Classifications

• H10W72/5445

  being orthogonal to a side surface of the chip, e.g. parallel arrangements · CPC title

• H10W72/5475

  multiple bond wires connected to common bond pads at both ends of the wires · CPC title

• H10W72/07554

  changes in dispositions · CPC title

• H10W72/547

  Dispositions of multiple bond wires · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title