Open block boundary group programming for non-volatile memory

Patent metadata

Field	Value
Publication number	US-12112814-B2
Application number	US-202217837345-A
Country	US
Kind code	B2
Filing date	Jun 10, 2022
Priority date	Jun 10, 2022
Publication date	Oct 8, 2024
Grant date	Oct 8, 2024

Abstract

Technology for open block boundary group programming of non-volatile memory such as NAND. The open block boundary group could potentially be read in response to a request from a host for the data stored in the group. In an aspect, the memory system will determine whether programming a group of memory cells in a selected block will result in an open block. If it will not result in an open block, then the memory system uses a first set of programming parameters to program the group. However, if it will result in an open block then the memory system uses a second set of programming parameters to program the boundary group. The programming parameters may include verify levels and/or a program voltage step size. The second set of programming parameters can tighten Vt distributions, which mitigates mis-reads if the boundary group is read.

First claim

What is claimed is:

1. An apparatus comprising:
one or more control circuits configured to connect to a three-dimensional memory structure comprising blocks, each block having a plurality of word lines and NAND strings associated with the word lines, wherein the one or more control circuits are configured to:
receive data from a host; and
program the data into groups of memory cells in a selected block, wherein each group of memory cells resides on a group of the NAND strings and is connected to a word line in the selected block, including:
program non-boundary groups of memory cells connected to a first set of one or more word lines in the selected block with a first set of program parameters responsive to a determination that at least one more group of the groups of memory cells is yet to be programmed with the data; and
program one or more boundary groups of the memory cells connected to a second set of one or more word lines in the selected block with a second set of program parameters responsive to a determination that there will be an unprogrammed group of memory cells in the selected block adjacent to each of the one or more boundary groups after programming the data from the host.

2. The apparatus of claim 1 , wherein:
programming the one or more boundary groups with the second set of program parameters results in boundary group threshold voltage (Vt) distributions; and
programming the non-boundary groups with the first set of program parameters results in non-boundary group Vt distributions, wherein individual Vt distributions of the boundary group threshold voltage distributions are tighter than corresponding individual Vt distributions of the non-boundary group Vt distributions.

3. The apparatus of claim 1 , wherein:
the first set of program parameters comprises a first set of verify voltages, wherein each verify voltage in the first set of verify voltages verifies memory cells being programmed to a different target state; and
the second set of program parameters comprises a second set of verify voltages that also verify memory cells being programmed to the different target states, wherein the verify voltages in the second set of verify voltages test for higher threshold voltages than corresponding verify voltages in the first set of verify voltages.

4. The apparatus of claim 3 , wherein:
the first set of program parameters further comprises a first program voltage step size; and
the second set of program parameters further comprises a second program voltage step size that is smaller than the first program voltage step size.

5. The apparatus of claim 1 , wherein:
the first set of program parameters further comprises a first program voltage step size; and
the second set of program parameters further comprises a second program voltage step size that is smaller than the first program voltage step size.

6. The apparatus of claim 1 , wherein the one or more control circuits are further configured to:
read a first boundary group of the one or more boundary groups in response to a request from a host prior to programming any data into the unprogrammed group adjacent to the first boundary group.

7. The apparatus of claim 1 , wherein the one or more control circuits are further configured to:
determine whether programming a unit of the data from the host will result in the one or more boundary groups based on how much of the received data remains to be programmed into groups of memory cells in the selected block.

8. The apparatus of claim 1 , wherein the one or more control circuits are configured to program the groups of memory cells to multiple bits per memory cell.

9. The apparatus of claim 1 , wherein the one or more control circuits are configured to program the groups of memory cells to a single bit per memory cell.

10. The apparatus of claim 1 , wherein the second set of program parameters depends on a location of the one or more boundary groups along the set of NAND strings.

11. A method for programming memory cells in a three-dimensional memory structure, wherein the memory cells are arranged as blocks having NAND strings and word lines associated with the NAND strings, the method comprising:
determining whether programming user data into respective groups of memory cells connected to the word lines in a selected block will result in an open block after programming the user data;
programming a first unit of the user data into a first group of memory cells connected to a first word line with a first set of program parameters responsive to a determination that programming the first group of memory cells will not result in an open block; and
programming a second unit of the user data into a second group of memory cells connected to a second word line with a second set of program parameters responsive to a determination that programming the second group of memory cells will result in an open block.

12. The method of claim 11 , wherein:
programming the first group of memory cells with the first set of program parameters comprises verifying the first group of memory cells using a first set of verify levels, wherein each verify level in the first set verifies memory cells being programmed to a different target state; and
programming the second group of memory cells with a second set of program parameters comprises verifying the second group of memory cells using a second set of verify levels that also verify memory cells being programmed to the different target states, wherein the second set of verify levels are upshifted from the first set of verify levels.

13. The method of claim 12 , wherein:
programming the first group of memory cells with the first set of program parameters comprises increasing a magnitude of a program voltage by a first step size from one program loop to a next program loop; and
programming the second group of memory cells with the second set of program parameters comprises increasing a magnitude of the program voltage by a second step size from one program loop to a next program loop, wherein the second step size is smaller than the first step size.

14. The method of claim 11 , wherein:
programming the first group of memory cells with the first set of program parameters comprises increasing a magnitude of a program voltage by a first step size from one program loop to a next program loop; and
programming the second group of memory cells with the second set of program parameters comprises increasing a magnitude of the program voltage by a second step size from one program loop to a next program loop, wherein the second step size is smaller than the first step size.

15. A non-volatile storage system comprising
a three-dimensional memory structure comprising blocks comprising vertically oriented NAND strings having memory cells, each block comprising a plurality of word lines; and
one or more control circuits in communication with the three-dimensional memory structure, wherein the one or more control circuits are configured to:
receive data from a host;
determine whether the data is sufficient to program an entire block of memory cells, wherein the block will be an open block if the data is insufficient to program the entire block; and
responsive to a determination that the block will be an open block, program the data into consecutive word lines in the open block including:
program units of the data into memory cells connected to non-boundary word lines in the open block with a first set of program parameters; and
program one or more units of the data into memory cells connected to a boundary word line in the open block with a second set of program par

Assignees

• Western Digital Tech Inc
• Sandisk Technologies Inc

Inventors

• Zhang Ke
• Wang Ming
• Li Liang

Classifications

• G11C16/102

  External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/3404

  Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells · CPC title

• G11C16/3459 Primary

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title