Read disturb detection in open blocks

Patent metadata

Field	Value
Publication number	US-9530517-B2
Application number	US-201514717582-A
Country	US
Kind code	B2
Filing date	May 20, 2015
Priority date	May 20, 2015
Publication date	Dec 27, 2016
Grant date	Dec 27, 2016

Abstract

A storage device with a memory may include read disturb detection for open blocks. An open or partially programmed block may develop read disturb errors from reading of the programmed portion of the open block. The detection of any read disturb effects may be necessary for continued programming of the open block and may include verifying that wordlines in the unprogrammed portion of the open block are in the erase state. A modified erase verify operation for the open block is used in which programmed wordlines are subject to a higher erase verify read voltage, while the unprogrammed wordlines are subject to an erase verify bias voltage.

First claim

We claim:

1. A method for programming a block comprising:
programming the block such that some wordlines are programmed and some wordlines are not programmed;
receiving a request to continue programming of the wordlines that are not programmed; and
performing a block level erase verify operation on all of the wordlines, wherein the erase verify operation biases the programmed wordlines differently from the not programmed wordlines.

2. The method of claim 1 wherein the block level erase verify operation is performed for the block and not performed wordline by wordline.

3. The method of claim 1 wherein the block comprises an open block until all wordlines in the block are programmed.

4. The method of claim 1 wherein the programmed wordlines are biased at a higher voltage.

5. The method of claim 4 wherein the higher voltage is a read voltage.

6. The method of claim 1 wherein the not programmed wordlines are biased at an erase voltage.

7. The method of claim 6 wherein the erase voltage is a negative voltage level.

8. The method of claim 1 further comprising:
counting, from the erase verify operation, a number of cells from the non-programmed wordlines that are not in an erase state; and
determining whether the counted number of cells exceeds a threshold.

9. The method of claim 8 further comprising:
continuing, in response to the request, the programming of the block when the counted number of cells is less than the threshold.

10. The method of claim 8 further comprising:
preventing further programming of the block when the counted number of cells exceeds the threshold by declining the request to continue programming.

11. The method of claim 1 wherein the method is performed with flash memory and the flash memory comprises a three-dimensional (3D) memory configuration, and wherein a controller is associated with operation of and storing to the flash memory.

12. A storage device comprising:
a non-volatile memory with blocks of memory, wherein at least one of the blocks is a partially programmed block;
an erase verification module that performs an erase verification operation on the partially programmed block with two different voltage levels depending on whether a wordline in the partially programmed block is programmed or not programmed; and
a read disturb detection module that prevents continued programming of the partially programmed block when the erase verification operation fails.

13. The storage device of claim 12 wherein the erase verification operation includes a read voltage applied to programmed wordlines of the partially programmed block and an erase verification voltage applied to non-programmed wordlines of the partially programmed block.

14. The storage device of claim 13 wherein the erase verification operation fails when a number of cells from the non-programmed wordlines of the partially programmed block that are not in an erase state exceeds a threshold.

15. The storage device of claim 14 wherein read operations for programmed wordlines of the partially programmed block cause a read disturb of non-programmed wordlines of the partially programmed block.

16. The storage device of claim 12 wherein the non-volatile memory is three bit per cell memory.

17. A method for detecting read disturb in a block comprising:
partially programming the block;
performing, prior to continuing programming of the partially programmed block, a modified erase verify operation on the block that determines a number of unprogrammed cells of the block that are not in an erase state; and
determining the read disturb of the block is excessive when the number of the unprogrammed cells of the block that are not in an erase state exceeds a threshold.

18. The method of claim 17 wherein the modified erase verify operation comprises biasing programmed wordlines from the block at a high voltage and biasing non-programmed wordlines from the block at a low voltage.

19. The method of claim 18 wherein the low voltage comprises an erase voltage level and the high voltage comprises a read voltage level.

20. The method of claim 17 wherein the threshold depends on a type of memory of the block or an intended usage of the block.

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Lee Aaron
• Zhou Zhenming
• Kochar Mrinal
• Hsu Cynthia Hua-Ling

Classifications

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/3418

  Disturbance prevention or evaluation; Refreshing of disturbed memory data · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/3427

  Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written · CPC title

• G11C16/16

  for erasing blocks, e.g. arrays, words, groups · CPC title