Method and system of enhanced reliability and error immunity in flash storage

Patent metadata

Field	Value
Publication number	US-10198217-B2
Application number	US-201615343546-A
Country	US
Kind code	B2
Filing date	Nov 4, 2016
Priority date	Nov 4, 2016
Publication date	Feb 5, 2019
Grant date	Feb 5, 2019

Abstract

A last written page in an open block in NAND flash is identified where the NAND flash includes a plurality of pages and the last written page has first content. Second content is written to an adjacent page in the open block, wherein the adjacent page is physically adjacent to the last written page in the open block and the second content enhances robustness of the first content.

First claim

What is claimed is:

1. A system, comprising:
a memory including negative AND (NAND) flash, the NAND flash comprising a plurality of pages; and
a NAND flash controller, wherein the NAND flash controller includes a processor and is configured to:
identify a last written page in an open block in the NAND flash, the last written page having first content; and
write second content to an adjacent page in the open block, wherein:
the adjacent page is physically adjacent to the last written page in the open block;
the second content enhances robustness of the first content; and
the adjacent page is written in response to a criteria associated with a time threshold and a second criteria associated with an error correction decoding result both being satisfied.

2. The system of claim 1 , further comprising a plurality of NAND flash, wherein the system includes a solid state drive (SSD).

3. The system of claim 1 , wherein to identify the last written page includes to:
write a page of a write job to the open block in the NAND flash;
determine whether the written page is a last page of the write job;
in the event that it is determined that the written page is the last page of the write job, flag the written page as the last written page and start a timer; and
determine whether the timer exceeds or meets the time threshold, wherein the second content is written to the adjacent page in the event it is determined that the timer exceeds or meets the time threshold.

4. The system of claim 1 , wherein to identify the last written page includes to:
write a page of a write job to the open block in the NAND flash;
determine whether the written page is a last page of the write job;
in the event it is determined that the written page is the last page of the write job, flag the written page as the last written page and start a timer;
determine whether the timer exceeds or meets a time threshold; and
in the event it is determined that the timer exceeds or meets the time threshold:
read the last written page to obtain a read page and perform error correction decoding on the read page to obtain a number of errors;
determine whether the error correction decoding has failed, wherein the second content is written to the adjacent page in the event it is determined that the error correction decoding has failed; and
in the event it is determined that the error correction decoding is successful, determine whether the number of errors exceeds or meets an error threshold, wherein the second content is written to the adjacent page in the event it is determined that the number of errors exceeds or meets the error threshold.

5. The system of claim 1 , wherein:
to write the second content to the adjacent page includes to write a pseudorandom sequence to the adjacent page; and
the NAND flash controller is further configured to:
generate a single parity check sequence based at least in part on the last written page and one or more previously written pages; and
write the single parity check sequence to an intervening page which is between the last written page and the adjacent page in a write sequence, wherein pages which are sequentially adjacent to each other in the write sequence are not necessarily physically adjacent to each other.

6. The system of claim 1 , wherein:
to write the second content to the adjacent page includes to write a pseudo-random binary sequence to the adjacent page; and
the NAND flash controller is further configured to:
generate a single parity check sequence based at least in part on the last written page and one or more previously written pages;
write the single parity check sequence to an intervening page which is between the last written page and the adjacent page in a write sequence, wherein pages which are sequentially adjacent to each other in the write sequence are not necessarily physically adjacent to each other;
read the last written page to obtain a read page and perform error correction decoding on the read page to obtain a number of errors;
determine whether the error correction decoding has failed, wherein in the event it is determined that the error correction decoding has failed, recovered data for the last written page is generated and the recovered data is written to the last written page; and
in the event it is determined that error correction decoding is successful, determine whether the number of errors exceeds or meets an error threshold, wherein in the event it is determined that the number of errors exceeds or meets the error threshold, error corrected data is written to the last written page.

7. The system of claim 1 , wherein the memory is configured to provide the processor with further instructions which when executed cause the processor to:
receive a write job to write to one or more pages;
determine a least number of open pages associated a plurality of open blocks; and
determine whether the number of pages in the write job exceeds or meets the least number of open pages, wherein in the event it is determined that the number of pages in the write job exceeds or meets the least number of open pages:
an open block with the least number of open pages is selected from the plurality of open blocks in order to obtain a selected open block; and
the write job is written to the selected open block.

8. The system of claim 1 , wherein the memory is configured to provide the processor with further instructions which when executed cause the processor to:
determine a number of erased blocks in a free block pool from which blocks are selected to be written to;
determine whether the number of erased blocks is less than or equal to a threshold number of erased blocks; and
in the event it is determined that the number of erased blocks is less than the threshold number of erased blocks, erase an empty block so that the erased block is added to the free block pool.

9. The system of claim 1 , wherein to write the second content to the adjacent page includes to:
record, in a bitmap associated with the open block, an indication that the last written page includes valid data; and
record, in the bitmap, an indication that the adjacent page includes invalid data.

10. The system of claim 1 , wherein to write the second content to the adjacent page includes to:
generate a single parity check sequence based at least in part on the last written page and one or more previously written pages;
write the single parity check sequence to an intervening page that is between the last written page and the adjacent page in a write sequence, wherein pages which are sequentially adjacent to each other in the write sequence are not necessarily physically adjacent to each other;
write a pseudorandom binary sequence to the adjacent page;
record, in a bitmap associated with the open block, an indication that the last written page contains valid data;
record, in the bitmap, an indication that the adjacent page includes invalid data; and
record, in the bitmap, an indication that the intervening page includes invalid data.

11. A method, comprising:
using a negative AND (NAND) flash controller to identify a last written page in an open block in NAND flash, wherein:
the NAND flash includes a plurality of pages; and
the last written page has first content; and

using the NAND flash controller to write second content to an adjacent page in the open block, wherein:
the adjacent page is physically adjacent to the last written page in the open block;
the second content enhances robustness of the first content; and
the adjacent page is written in response to a criteria associated with a time threshold and a second criteria associated with an error correctio

Assignees

• Alibaba Group Holding Ltd

Inventors

• Li Shu

Classifications

• G06F11/1068 Primary

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title

• G06F3/0659 Primary

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0619

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G06F3/064

  Management of blocks · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title