Vertical transistor fabrication for memory applications

Patent metadata

Field	Value
Publication number	US-12108604-B2
Application number	US-202117479789-A
Country	US
Kind code	B2
Filing date	Sep 20, 2021
Priority date	Feb 1, 2019
Publication date	Oct 1, 2024
Grant date	Oct 1, 2024

Abstract

Embodiments of the present disclosure provide an apparatus and methods for forming stair-like structures with accurate profiles and dimension control for manufacturing three dimensional (3D) stacked memory cell semiconductor devices. In one embodiment, a memory cell device includes a film stack comprising alternating pairs of dielectric layers and conductive structures horizontally formed on a substrate, an opening formed in the film stack, wherein the opening is filled with a channel layer and a center filling layer, and a protective liner layer disposed between the conductive structure and the channel layer.

First claim

The invention claimed is:

1. A method of memory device on a substrate comprises:
forming an opening in a film stack including a first layer and a second layer;
filling the opening with one or more layers, wherein the one or more layers comprise a channel layer, the channel layer having a sidewall adjacent the first layer and the second layer;
selectively removing the first layer from the film stack to create a space and expose a portion of the sidewall of the channel layer;
selectively oxidizing the portion of the sidewall of the channel layer to form a protective liner layer; and
filling the space with a conductive structure.

2. The method of claim 1 , wherein the first layer is a silicon nitride layer and the second layer is a silicon oxide layer.

3. The method of claim 1 , wherein selective oxidizing the portion of the channel layer further comprises:
performing a radical plasma oxidation to oxidize the channel layer.

4. The method of claim 1 , wherein the channel layer is a silicon containing material.

5. The method of claim 1 , wherein the conductive structure comprises a metal containing material and a ferroelectric layer.

6. The method of claim 5 , wherein the ferroelectric layer is fabricated from high dielectric constant material.

7. The method of claim 5 , wherein high dielectric constant material is selected from a group consisting of at least one of hafnium containing materials, zirconium dioxide (ZrO 2 ), zirconium silicon oxide (ZrSiO 2 ), tantalum dioxide (Ta 2 O 5 ), aluminum oxide (Al 2 O 3 ), bismuth strontium titanium (BST), and platinum zirconium titanium (PZT).

8. The method of claim 5 , wherein the protective liner layer is in direct contact with the ferroelectric layer.

9. The method of claim 8 , wherein the protective liner layer is a silicon oxide layer.

10. A method of forming stair-like structures on a substrate comprises:
selectively oxidizing an outer side portion of a channel layer exposed by a space defined between dielectric layers formed in a film stack, wherein the film stack has a center opening filled by a multi-layer structure comprising the channel layer;
forming a protective liner layer on the outer side portion of the channel layer; and
forming a ferroelectric layer in contact with the protective liner layer, wherein the ferroelectric layer is a high dielectric constant material.

Assignees

• Applied Materials Inc

Inventors

• Ahn Jaesoo
• Kwon Thomas
• Pakala Mahendra

Classifications

• H10P50/283

  by chemical means · CPC title

• H10P14/6319

  Formation by plasma treatments, e.g. plasma oxidation of the substrate · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/27

  using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials · CPC title

• H10P14/24

  using chemical vapour deposition [CVD] · CPC title