Semiconductor device manufacturing method comprising first conductive layer with increased roughness in array region

Patent metadata

Field	Value
Publication number	US-12108594-B2
Application number	US-202117370503-A
Country	US
Kind code	B2
Filing date	Jul 8, 2021
Priority date	Aug 14, 2020
Publication date	Oct 1, 2024
Grant date	Oct 1, 2024

Abstract

A semiconductor manufacturing method includes: providing a semiconductor substrate, in which the semiconductor substrate includes an array region and a peripheral circuit region, in the array region, multiple capacitor contact holes are on the semiconductor substrate, and a first conductive layer is deposited on a bottom of each of the capacitor contact hole, and in the peripheral circuit region, a device layer is on the semiconductor substrate; treating the first conductive layer to increase its roughness; forming wire contact holes exposing the semiconductor substrate in the peripheral circuit region; forming a transition layer that at least covers a surface of the first conductive layer and a surface of the semiconductor substrate exposed by the wire contact holes; and forming a second conductive layer that covers the transition layer, and fills the capacitor contact holes and the wire contact holes.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor structure, comprising:
providing a semiconductor substrate which comprises an array region and a peripheral circuit region, wherein in the array region, multiple capacitor contact holes are provided on the semiconductor substrate, and a first conductive layer is deposited on a bottom of each of the capacitor contact holes, and in the peripheral circuit region, a device layer is on the semiconductor substrate;
treating the first conductive layer to increase roughness of the first conductive layer;
forming wire contact holes exposing the semiconductor substrate in the peripheral circuit region;
wherein a surface roughness of the first conductive layer in the capacitor contact holes is greater than a surface roughness of the semiconductor substrate exposed by the wire contact holes;
forming a transition layer, wherein the transition layer of the array region covers at least the surface of the first conductive layer, and the transition layer of the peripheral circuit region is embedded in the semiconductor substrate exposed by the wire contact holes;
wherein a thickness of the transition layer located in the array region is greater than that of the transition layer located in the peripheral circuit region; and
forming a second conductive layer covering the transition layer, and filling the capacitor contact holes and the wire contact holes.

2. The method for manufacturing the semiconductor structure of claim 1 , further comprising:
forming multiple discrete bit line structures on the semiconductor substrate;
providing the capacitor contact holes respectively between the bit line structures; and
prior to said treating the first conductive layer, thinning the bit line structure of the array region and the device layer of the peripheral circuit region.

3. The method for manufacturing the semiconductor structure of claim 2 , wherein
each of the bit line structures comprises a bit line contact island and a bit line, wherein the bit line contact island contacts the semiconductor substrate, the bit line is arranged on the bit line contact island, and the bit line comprises a conductive layer and a dielectric layer disposed on the conductive layer, wherein the dielectric layer is thinned in said thinning.

4. The method for manufacturing the semiconductor structure of claim 1 , wherein
said treating the first conductive layer further comprises performing ion implantation to the first conductive layer, to damage a surface evenness of the first conductive layer, thereby increasing the roughness of the first conductive layer.

5. The method for manufacturing the semiconductor structure of claim 4 , wherein
the first conductive layer is a polysilicon layer, and said performing the ion implantation to the first conductive layer is of performing germanium ion, carbon ion or arsenic ion implantation to the first conductive layer.

6. The method for manufacturing the semiconductor structure of claim 1 , further comprising:
forming an isolation layer, which covers a surface of the array region and a surface of the peripheral circuit region after said treating the first conductive layer;
and removing the isolation layer after said forming the wire contact holes in the peripheral circuit region.

7. The method for manufacturing the semiconductor structure of claim 1 , wherein
said forming the transition layer further comprises:
depositing a cobalt layer, wherein at the bottom of each of the capacitor contact hole and a bottom of each of the wire contact hole, cobalt reacts with the first conductive layer and the semiconductor substrate to form the transition layer; and
performing a rapid thermal process.

8. The method for manufacturing the semiconductor structure of claim 1 , wherein
the second conductive layer comprises an adhesion layer and a metal conductive layer, and said forming the second conductive layer further comprises:
forming the adhesion layer on a surface of the transition layer; and
forming the metal conductive layer on a surface of the adhesion layer, wherein the metal conductive layer fills the capacitor contact holes and the wire contact holes.

Assignees

• Changxin Memory Tech Inc

Inventors

• Lu Jingwen
• Zhu Bingyu
• Bai Shijie

Classifications

• H10D30/60

  Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence) · CPC title

• H10B12/482

  Bit lines · CPC title

• H10B12/50

  Peripheral circuit region structures · CPC title

• H10B12/30

  DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells · CPC title

• H10B12/03

  Making the capacitor or connections thereto · CPC title