Wafer storage system

US12103772B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12103772-B2
Application numberUS-202217847542-A
CountryUS
Kind codeB2
Filing dateJun 23, 2022
Priority dateAug 30, 2021
Publication dateOct 1, 2024
Grant dateOct 1, 2024

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A wafer storage system includes a main rail, an overhead hoist transport (OHT) on the main rail, the OHT being configured to transfer at least one storage case with wafers, an interface port on at least one side of the main rail, an auxiliary rail on one side of the interface port, the auxiliary rail being parallel to the main rail, and the interface port being between the main rail and the auxiliary rail, an auxiliary transport on the auxiliary rail, the auxiliary transport being configured to move along the auxiliary rail and to move the at least one storage case, a storage shelf on at least one side of the auxiliary transport, the storage shelf being configured to store the at least one storage case, and a worktable on one side of the storage shelf, the storage shelf being between the worktable and the auxiliary transport.

First claim

Opening claim text (preview).

What is claimed is: 1. A wafer storage system provided in a semiconductor factory, comprising: a main rail; an overhead hoist transport (OHT) on the main rail, the OHT being configured to transfer at least one storage case with wafers; an interface port on at least one side of the main rail; an auxiliary rail on one side of the interface port, the auxiliary rail being parallel to the main rail, and the interface port being between the main rail and the auxiliary rail; an auxiliary transport on the auxiliary rail, the auxiliary transport being configured to move along the auxiliary rail and to move the at least one storage case; a storage shelf on at least one side of the auxiliary transport, the storage shelf being configured to store the at least one storage case; and a worktable on one side of the storage shelf, the storage shelf being between the worktable and the auxiliary transport, the worktable including a frame, a plate attached to the frame, the plate being configured to support an operator, and a ladder connected to the plate; wherein the interface port, the auxiliary rail, the storage shelf, and the worktable are attached in a non-moveable manner to a ceiling surface of the semiconductor factory to maintain a fixed positional relationship to the ceiling surface. 2. The wafer storage system as claimed in claim 1 , wherein the interface port includes an empty space, the empty space being configured to accommodate a plurality of storage cases. 3. The wafer storage system as claimed in claim 1 , wherein the auxiliary transport is movable between the interface port and the storage shelf, the auxiliary transport being configured to move the at least one storage case between the interface port and the storage shelf. 4. The wafer storage system as claimed in claim 3 , wherein the auxiliary transport includes: a traveling unit on the auxiliary rail, the traveling unit being configured to move along the auxiliary rail; a slider connected to the traveling unit, the slider being slidably movable between the interface port and the storage shelf along a direction intersecting the auxiliary rail; and a gripper below the slider, the gripper being moveable along a direction normal to the auxiliary rail to grip the storage case. 5. The wafer storage system as claimed in claim 4 , wherein a movable distance of the slider in a direction intersecting the auxiliary rail is longer than a movable distance of the OHT in a direction intersecting the main rail. 6. The wafer storage system as claimed in claim 1 , wherein the storage shelf includes a purge gas injection pipe to inject a purge gas. 7. The wafer storage system as claimed in claim 1 , wherein the storage shelf includes: a first storage shelf on one side of the auxiliary transport; and a second storage shelf connected to the first storage shelf, the second storage shelf being below the auxiliary transport. 8. The wafer storage system as claimed in claim 7 , wherein a width of the first storage shelf is at least twice a width of the second storage shelf, as measured along a direction intersecting the main rail. 9. The wafer storage system as claimed in claim 7 , wherein the first storage shelf includes a first storage space configured to accommodate a plurality of rows and columns of storage cases, and the second storage shelf includes a second storage space configured to accommodate a single column of storage cases. 10. The wafer storage system as claimed in claim 1 , wherein the frame of the worktable is attached to the ceiling surface of a semiconductor factory. 11. The wafer storage system as claimed in claim 1 , wherein the interface port, the auxiliary transport, the storage shelf, and the worktable are sequentially disposed on one side or both sides of the OHT, with respect to the OHT. 12. The wafer storage system as claimed in claim 1 , further comprising a controller connected to the OHT and the auxiliary transport, the controller being configured to control movement of the OHT and the auxiliary transport. 13. A wafer storage system provided in a semiconductor factory, comprising: a main rail; an overhead hoist transport (OHT) on the main rail, the OHT being configured to transfer at least one storage case with wafers; an interface port on at least one side of the main rail; an auxiliary rail on one side of the interface port; an auxiliary transport on the auxiliary rail, the auxiliary transport being configured to move along the auxiliary rail; a storage shelf on at least one side of the auxiliary transport, the storage shelf being configured to store the at least one storage case, and the storage shelf including: a first storage shelf on one side of the auxiliary transport, and a second storage shelf connected to the first storage shelf, the second storage shelf being below the auxiliary transport, and the auxiliary transport being configured to transfer the at least one storage case between the interface port and at least one of the first storage shelf and the second storage shelf, and a worktable on one side of the storage shelf, the worktable including a frame, a plate attached to the frame, the plate being configured to support an operator, and a ladder connected to the plate, wherein the interface port, the auxiliary rail, the first storage shelf, the second storage shelf and the worktable are attached in a non-moveable manner to a ceiling surface of the semiconductor factory, and wherein the first storage shelf is disposed directly adjacent to the worktable and between the worktable and the auxiliary transport to maintain a fixed positional relationship to the ceiling surface. 14. The wafer storage system as claimed in claim 13 , wherein the interface port, the auxiliary transport, the first storage shelf, and the worktable are sequentially disposed on one side or both sides of the OHT, with respect to the OHT. 15. The wafer storage system as claimed in claim 13 , further comprising a controller connected to the OHT and the auxiliary transport, the controller being configured to control movement of the OHT and the auxiliary transport.

Assignees

Inventors

Classifications

  • Storage means · CPC title

  • Conveying cassettes, containers or carriers · CPC title

  • Loading to or unloading from a conveyor · CPC title

  • Overhead conveying · CPC title

  • Transporting devices for sheet glass · CPC title

Patent family

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Frequently asked questions

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What does patent US12103772B2 cover?
A wafer storage system includes a main rail, an overhead hoist transport (OHT) on the main rail, the OHT being configured to transfer at least one storage case with wafers, an interface port on at least one side of the main rail, an auxiliary rail on one side of the interface port, the auxiliary rail being parallel to the main rail, and the interface port being between the main rail and the aux…
Who is the assignee on this patent?
Samsung Electronics Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10P72/3404. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Oct 01 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 10 related publications on this page (citations in our corpus or others sharing the same primary CPC).