Semiconductor memory devices having an electrode with an extension

Patent metadata

Field	Value
Publication number	US-12102020-B2
Application number	US-202217647006-A
Country	US
Kind code	B2
Filing date	Jan 4, 2022
Priority date	Jan 4, 2022
Publication date	Sep 24, 2024
Grant date	Sep 24, 2024

Abstract

A semiconductor memory device is provided. The memory device includes a first electrode, a resistive layer, and a second electrode. The resistive layer is arranged over the first electrode. The second electrode is arranged over the resistive layer. The second electrode includes a lower surface and an extension extending from under the lower surface. The extension is at least partially arranged within the resistive layer.

First claim

What is claimed is:

1. A memory device, comprising:
a first electrode;
a resistive layer over the first electrode; and
a second electrode over the resistive layer, the second electrode comprises a lower surface and an extension extending from under the lower surface and at least partially arranged within the resistive layer.

2. The memory device of claim 1 , wherein the extension of the second electrode has tapered side surfaces that converge to a corner.

3. The memory device of claim 1 , wherein the resistive layer comprises an upper surface, and the upper surface of the resistive layer share a same plane as the lower surface of the second electrode.

4. The memory device of claim 1 , wherein the second electrode is partially arranged over the resistive layer.

5. The memory device of claim 4 , wherein the second electrode comprises a side surface, and the extension of the second electrode extends from the side surface and partially into the resistive layer.

6. The memory device of claim 1 , wherein the second electrode comprises a first portion having a first thickness and a second portion having a second thickness, the second thickness is thicker than the first thickness and the second portion comprises the extension.

7. The memory device of claim 1 , wherein the first electrode has an upper surface, and the resistive layer is arranged within and overlays a portion of the upper surface of the first electrode.

8. The memory device of claim 1 , wherein the first electrode has an upper surface, and the memory device further comprises an insulating layer arranged partially over the upper surface of the first electrode and at laterally opposite sides of the resistive layer.

9. The memory device of claim 8 , wherein the insulating layer comprises an electrically insulative material and the resistive layer comprises another electrically insulative material, and the electrically insulative material of the insulating layer has a higher dielectric breakdown voltage than the electrically insulative material of the resistive layer.

10. The memory device of claim 8 , wherein the insulating layer and the resistive layer have a substantially equal thickness.

11. A memory device, comprising:
a first dielectric layer;
a first electrode in the first dielectric layer;
a resistive layer over the first electrode;
a second dielectric layer over the resistive layer; and
a second electrode in the second dielectric layer, the second electrode is partially arranged over the resistive layer and comprises an extension at least partially arranged within the resistive layer.

12. The memory device of claim 11 , wherein the resistive layer comprises a portion arranged under the extension.

13. The memory device of claim 11 , wherein the resistive layer and the second dielectric layer consist essentially of the same electrically insulative material.

14. The memory device of claim 13 , wherein the electrically insulative material is silicon oxide.

15. The memory device of claim 11 , wherein the resistive layer and the second dielectric layer comprises an electrically insulative material having different densities.

16. The memory device of claim 15 , wherein the resistive layer comprises a first portion having a first density and a second portion having a second density under the first portion, the second density is lower than the first density.

17. The memory device of claim 11 , wherein the first electrode is a via structure.

18. The memory device of claim 11 , wherein the second electrode is a line structure.

19. A method of forming a memory device, comprising:
forming a first electrode;
forming a resistive layer over the first electrode;
forming a dielectric layer over the resistive layer;
forming a trench and in the dielectric layer and a trench extension at least partially within the resistive layer; and
forming a second electrode in the trench and the trench extension.

20. The method of claim 19 , wherein forming the trench and the trench extension comprises concurrently removing a portion of the dielectric layer and a portion of the resistive layer to form the trench and the trench extension, respectively.

Assignees

• Globalfoundries Sg Pte Ltd

Inventors

• Sun Jianxun
• Chockalingam Ramasamy
• Tan Juan Boon

Classifications

• H10N70/8418

  adapted for focusing electric field or current, e.g. tip-shaped · CPC title

• H10N70/826

  adapted for essentially vertical current flow, e.g. sandwich or pillar type devices · CPC title

• H10N70/063 Primary

  by etching of pre-deposited switching material layers, e.g. lithography · CPC title

• H10B63/80

  Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays · CPC title

• H10N70/245

  the species being metal cations, e.g. programmable metallization cells · CPC title