Push-pull output driver and operational amplifier using same

Patent metadata

Field	Value
Publication number	US-12101068-B2
Application number	US-202117349586-A
Country	US
Kind code	B2
Filing date	Jun 16, 2021
Priority date	Nov 20, 2018
Publication date	Sep 24, 2024
Grant date	Sep 24, 2024

Abstract

A voltage driver circuit for an output stage of an operational amplifier, or other circuits, includes a level shifter and an output driver including a source follower and a common source amplifier in a push-pull configuration. The level shifter generates a node voltage as a function of an input voltage on the input node. The output driver including a first transistor having a control terminal receiving the node voltage, and connected between a supply voltage and an output node, and a second transistor having a control terminal receiving the input voltage from the input node, and connected between the output node and a reference voltage, wherein the first and second transistors have a common conductivity type.

First claim

What is claimed is:

1. A voltage driver circuit, comprising:
an operational amplifier having an output terminal, which generates an input voltage;
a level shifter having an input node, which directly connects to the output terminal of the operational amplifier and receives the input voltage to generate a node voltage; and
a first transistor having a control terminal receiving the node voltage, and connected between a supply voltage and an output node, and a second transistor having a control terminal receiving the input voltage from the input node, and connected between the output node and a reference voltage, wherein the first and second transistors have a common conductivity type, wherein the first transistor is directly connected to the supply voltage,
wherein the level shifter includes a third transistor including (i) a control terminal directly receiving the input voltage from the input node and (ii) a current carrying node at which the node voltage is generated, the current carrying node of the third transistor being directly connected to the control terminal of the first transistor,
wherein the level shifter includes a bias current source including a fourth transistor, the fourth transistor and the third transistor being connected in series between the supply voltage and the reference voltage, and
wherein an input bias on a control terminal of the fourth transistor is generated from a source that is separate and independent from one or more sources influencing the input voltage generated by the operational amplifier, such that the input voltage is generated by the operational amplifier independently of the input bias on the control terminal of the fourth transistor.

2. The circuit of claim 1 , wherein the first and second transistors are field effect transistors.

3. The circuit of claim 1 , wherein the first transistor is configured as a source follower, and the second transistor is configured as a common source amplifier.

4. The circuit of claim 1 , wherein the level shifter is connected between the supply voltage and the reference voltage.

5. The circuit of claim 1 , wherein the first, second and third transistors are field effect transistors.

6. The circuit of claim 1 , wherein the first transistor is configured as a source follower, and the second transistor is configured in current mirror configuration with the third transistor.

7. The circuit of claim 1 , wherein the fourth transistor has a conductivity type different than the third transistor.

8. The circuit of claim 1 , wherein the first and second transistors are bipolar transistors.

9. The circuit of claim 8 ,
wherein the first transistor is configured as an emitter follower, and the second transistor is configured in current mirror configuration with the third transistor.

10. The voltage driver circuit of claim 1 , wherein the input bias on the control terminal of the fourth transistor is a bias voltage generated to provide immunity from process, voltage and temperature (PVT) variations.

11. An operational amplifier circuit, comprising:
an input stage having first and second inputs, which generates a first node voltage at a first circuit node as a function of voltages on the first and second inputs;
a level shifter directly connected to the first circuit node, which generates a second node voltage on a second circuit node as a function of the first node voltage; and
a first transistor having a control terminal receiving the second node voltage, and connected between a supply voltage and an output node, and a second transistor having a control terminal receiving the first node voltage from the first circuit node, and connected between the output node and a reference voltage, wherein the first and second transistors have a common conductivity type, wherein the level shifter is connected between the supply voltage and the reference voltage, and wherein the first transistor is directly connected to the supply voltage,
wherein the level shifter includes a third transistor including (i) a control terminal receiving the first node voltage from the first circuit node and (ii) a current carrying node at which the second node voltage is generated, the current carrying node of the third transistor being directly connected to the control terminal of the first transistor,
wherein the level shifter includes a bias current source including a fourth transistor, the fourth transistor and the third transistor being connected in series between the supply voltage and the reference voltage,
wherein an input bias on a control terminal of the fourth transistor is generated from a source that is separate and independent from one or more sources influencing the first node voltage generated by the input stage, such that the first node voltage is generated by the input stage independently of the input bias on the control terminal of the fourth transistor, and
wherein the control terminal of the first transistor is controlled only by the current carrying node of the third transistor and a current carrying path of the fourth transistor.

12. The circuit of claim 11 , wherein the first and second transistors are field effect transistors.

13. The circuit of claim 11 , wherein the first transistor is configured as a source follower, and the second transistor is configured as a common source amplifier.

14. The circuit of claim 11 , wherein the third transistor has the same conductivity type as the first and second transistors.

15. The circuit of claim 14 , wherein the fourth transistor has a conductivity type different than the third transistor.

16. The circuit of claim 14 , wherein the third transistor has a drain node connected to the second circuit node.

17. The circuit of claim 14 , wherein the first transistor is configured as a source follower, and the second transistor is configured in current mirror configuration with the third transistor.

18. The circuit of claim 11 ,
wherein the first and second transistors are bipolar transistors, and
wherein the first transistor is configured as an emitter follower, and the second transistor is configured in current mirror configuration with the third transistor.

19. The circuit of claim 11 , wherein the input stage comprises a differential amplifier.

20. A voltage driver circuit, comprising:
an amplifier having a first input and a second input, generating a voltage at a first circuit node based on a difference between voltages applied to the first and second inputs;
a first transistor connected between a supply voltage and an output node, and having a control terminal, wherein the first transistor is directly connected to the supply voltage;
a second transistor connected between the output node and a reference voltage, and having a control terminal connected to the first circuit node, wherein the first and second transistors have a common conductivity type;
a third transistor connected in current mirror relationship with the second transistor, and having (i) a control terminal directly receiving the voltage from the first circuit node and (ii) a first current carrying terminal at which a second voltage is generated, the first current carrying terminal being directly connected to the control terminal of the first transistor; and
a bias current source including a fourth transistor, the fourth transistor and the third transistor being connected in series between the supply voltage and the reference voltage,
wherein an input bias on a control terminal of the fourth transistor is generated from a source that is separate and

Assignees

• Macronix Int Co Ltd

Inventors

• Yang Yih-Shan

Classifications

• H03K3/26

  by the use, as active elements, of bipolar transistors with internal or external positive feedback (H03K3/023, H03K3/027 take precedence) · CPC title

• H03F3/45174

  Mirror types · CPC title

• H03F3/45273

  Mirror types · CPC title

• H03F3/45484

  in differential amplifiers with bipolar transistors as the active amplifying circuit (H03F3/4578 takes precedence) · CPC title

• H03K3/356034

  the input circuit having a differential configuration · CPC title