Arsenic-doped epitaxial source/drain regions for NMOS

Patent metadata

Field	Value
Publication number	US-12094881-B2
Application number	US-202318108526-A
Country	US
Kind code	B2
Filing date	Feb 10, 2023
Priority date	Sep 28, 2018
Publication date	Sep 17, 2024
Grant date	Sep 17, 2024

Abstract

Techniques are disclosed for providing an integrated circuit structure having NMOS transistors including an arsenic-doped interface layer between epitaxially grown source/drain regions and a channel region. The arsenic-doped interface layer may include, for example, arsenic-doped silicon (Si:As) having arsenic concentrations in a range of about 1E20 atoms per cm 3 to about 5E21 atoms per cm 3 . The interface layer may have a relatively uniform thickness in a range of about 0.5 nm to full fill where the entire source/drain region is composed of the Si:As. In cases where the arsenic-doped interface layer only partially fills the source/drain regions, another n-type doped semiconductor material can fill remainder (e.g., phosphorus-doped III-V compound or silicon). The use of a layer having a high arsenic concentration can provide improved NMOS performance in the form of abrupt junctions in the source/drain regions and highly conductive source/drain regions with negligible diffusion of arsenic into the channel region.

First claim

What is claimed is:

1. An integrated circuit structure, comprising:
a bulk silicon substrate;
a gate structure over the bulk silicon substrate, the gate structure being part of an NMOS transistor device; and
a source region and a drain region to respective sides of the gate structure, the source region and the drain region each being a bi-layer structure including a first layer and a second layer, wherein the first layer includes an arsenic concentration in a range of 1E20 atoms per cm 3 to 5E21 atoms per cm 3 , and the second layer includes semiconductor fill.

2. The integrated circuit structure of claim 1 , wherein one or both the source region and the drain region includes a tip region that extends under the gate structure, and the first layer is in the tip region.

3. The integrated circuit structure of claim 1 , wherein the first layer has a thickness of at least 0.5 nm.

4. The integrated circuit structure of claim 1 , wherein the first layer comprises an arsenic concentration of 1E21 atoms per cm 3 , or higher.

5. The integrated circuit structure of claim 1 , wherein the first layer and the second layer include a compositionally same material.

6. The integrated circuit structure of claim 5 , wherein the compositionally same material is silicon, and the second layer is doped with arsenic, phosphorus, and/or carbon.

7. The integrated circuit structure of claim 6 , wherein the second layer comprises a carbon concentration in a range of 0.05 atomic percent to 3 atomic percent.

8. A method of fabricating an integrated circuit structure, the method comprising:
forming a gate structure over a bulk silicon substrate, the gate structure being part of an NMOS transistor device; and
forming a source region and a drain region to respective sides of the gate structure, the source region and the drain region each being a bi-layer structure including a first layer and a second layer, wherein the first layer includes an arsenic concentration in a range of 1E20 atoms per cm 3 to 5E21 atoms per cm 3 , and the second layer includes semiconductor fill.

9. The method of claim 8 , wherein one or both the source region and the drain region includes a tip region that extends under the gate structure, and the first layer is in the tip region.

10. The method of claim 8 , wherein the first layer has a thickness of at least 0.5 nm.

11. The method of claim 8 , wherein the first layer comprises an arsenic concentration of 1E21 atoms per cm 3 , or higher.

12. The method of claim 8 , wherein the first layer and the second layer include a compositionally same material.

13. The method of claim 12 , wherein the compositionally same material is silicon, and the second layer is doped with arsenic, phosphorus, and/or carbon.

14. The method of claim 13 , wherein the second layer comprises a carbon concentration in a range of 0.05 atomic percent to 3 atomic percent.

15. A method for forming an integrated circuit structure, the method comprising:
forming gate structure over a substrate, the gate structure being part of an NMOS transistor device;
forming a source region recess and a drain region recess to respective sides of the gate structure;
depositing an arsenic-doped interface layer in the source region recess and the drain region recess, the arsenic-doped interface layer including an arsenic concentration in a range of 1E20 atoms per cm.sup.3 to 5E21 atoms per cm 3 ;
forming a source region body on top of the arsenic-doped interface layer at least partially in the source region recess; and
forming a drain region body on top of the arsenic-doped interface layer at least partially in the drain region recess.

16. The method of claim 15 , wherein the arsenic-doped interface layer further comprises silicon.

17. The method of claim 15 , wherein the source region body comprises an n-type impurity.

Assignees

• Intel Corp

Inventors

• Murthy Anand
• Keech Ryan
• Minutillo Nicholas G
• Jhaveri Ritesh

Classifications

• H10D30/6219

  characterised by the source or drain electrodes · CPC title

• H10D84/0193

  the components including FinFETs · CPC title

• H10D84/0186

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D64/693

  the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials · CPC title