Light emitting structure

US12094864B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12094864-B2
Application numberUS-202318315758-A
CountryUS
Kind codeB2
Filing dateMay 11, 2023
Priority dateJun 17, 2013
Publication dateSep 17, 2024
Grant dateSep 17, 2024

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

Light emitting devices and methods of integrating micro LED devices into light emitting device are described. In an embodiment a light emitting device includes a reflective bank structure within a bank layer, and a conductive line atop the bank layer and elevated above the reflective bank structure. A micro LED device is within the reflective bank structure and a passivation layer is over the bank layer and laterally around the micro LED device within the reflective bank structure. A portion of the micro LED device and a conductive line atop the bank layer protrude above a top surface of the passivation layer.

First claim

Opening claim text (preview).

What is claimed is: 1. A light emitting structure comprising: a substrate; a plurality of reflective bank structures on the substrate, wherein each reflective bank structure functions as a bottom electrode; a bank layer over the substrate; a plurality of bank openings in the bank layer, each bank opening including a corresponding reflective bank structure; a group of vertical light emitting diode (LED) devices bonded to the plurality of reflective bank structures with a corresponding plurality of solder bonding layers; and a passivation layer spanning over the substrate and the bank layer, the passivation layer laterally surrounding the plurality of vertical LED devices. 2. The light emitting structure of claim 1 , wherein each vertical light emitting diode device in the plurality of vertical light emitting diode devices includes a micro p-n diode. 3. The light emitting structure of claim 1 , wherein each vertical light emitting diode device in the plurality of vertical light emitting diode devices has a maximum width of 1 μm-100 μm. 4. The light emitting structure of claim 3 , wherein each vertical light emitting diode device in the plurality of vertical light emitting diode devices has a maximum width of 1 μm-5 μm. 5. The light emitting structure of claim 3 , wherein each vertical light emitting diode device in the plurality of vertical light emitting diode devices has a maximum thickness of 5 μm or less. 6. The light emitting structure of claim 3 , wherein no vertical light emitting diode device of the plurality of vertical light emitting diode devices spans along a sidewall of a corresponding bank opening. 7. The light emitting structure of claim 3 , further comprising a top electrode layer spanning over the passivation layer and the plurality of vertical light emitting diode devices, and in electrical contact with the plurality of vertical light emitting diode devices. 8. The light emitting structure of claim 7 , wherein each reflective bank structure is coupled to a corresponding driving transistor. 9. The light emitting structure of claim 8 , further comprising an opening though the bank layer, wherein the top electrode layer is electrically connected with a ground tie line through the opening. 10. The light emitting structure of claim 8 , further comprising ground tie line over the bank layer and the passivation layer, wherein the top electrode layer is electrically connected with the ground tie line. 11. The light emitting structure of claim 8 , wherein each reflective bank structure of the plurality of reflective bank structures is reflective to the visible wavelength range of 380 nm-750 nm. 12. The light emitting structure of claim 11 , wherein each reflective bank structure includes a multiple-layer stack. 13. The light emitting structure of claim 12 , wherein the multiple-layer stack includes a metallic layer selected from the plurality consisting of silver, aluminum, and titanium. 14. The light emitting structure of claim 8 , wherein each reflective bank structure spans sidewalls of a corresponding bank opening. 15. The light emitting structure of claim 14 , wherein each bank structure includes a multiple-layer stack. 16. The light emitting structure of claim 15 , wherein the multiple-layer stack includes a metallic layer selected from the group consisting of silver, aluminum, and titanium.

Assignees

Inventors

Classifications

  • batch processes · CPC title

  • H10W90/00Primary

    Package configurations · CPC title

  • Connection of the pixel electrodes to the driving transistors · CPC title

  • Interconnections, e.g. wiring lines or terminals (connection of the pixel electrodes to the driving transistors H10H29/39) · CPC title

  • Interconnections (of active-matrix LED displays H10H29/49) · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US12094864B2 cover?
Light emitting devices and methods of integrating micro LED devices into light emitting device are described. In an embodiment a light emitting device includes a reflective bank structure within a bank layer, and a conductive line atop the bank layer and elevated above the reflective bank structure. A micro LED device is within the reflective bank structure and a passivation layer is over the b…
Who is the assignee on this patent?
Apple Inc
What technology area does this patent fall under?
Primary CPC classification H10W72/0198. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Sep 17 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).