LED display with wavelength conversion layer

Patent metadata

Field	Value
Publication number	US-9865577-B2
Application number	US-201715438587-A
Country	US
Kind code	B2
Filing date	Feb 21, 2017
Priority date	Jun 18, 2013
Publication date	Jan 9, 2018
Grant date	Jan 9, 2018

Abstract

A display and method of manufacture are described. The display may include a substrate including an array of pixels with each pixel including multiple subpixels, and each subpixel within a pixel is designed for a different color emission spectrum. An array of micro LED device pairs are mounted within each subpixel to provide redundancy. An array of wavelength conversion layers comprising phosphor particles are formed over the array of micro LED device pairs for tunable color emission spectrum.

First claim

What is claimed is:

1. A display panel comprising:
a display substrate including an array of pixels;
a first pixel of the array of pixels that includes a first subpixel designed for a first color emission spectrum, and a second subpixel designed for a second color emission spectrum different from the first color emission spectrum;
a first vertical light emitting diode (LED) mounted on a first bottom electrode within the first subpixel;
a second vertical LED mounted on a second bottom electrode within the second subpixel;
a sidewall passivation material that laterally surrounds the first and second vertical LEDs;
a top electrode layer that spans over the sidewall passivation layer material and the first and second vertical LEDs, and is in electrical contact with the first and second vertical LEDs;
a first wavelength conversion layer comprising phosphor particles over the top electrode layer and the first vertical LED, wherein the first wavelength conversion layer is not over the second vertical LED.

2. The display panel of claim 1 , wherein the display substrate further comprises a terminal line, and the top electrode layer electrically connects the first vertical LED and the second vertical LED to the terminal line.

3. The display panel of claim 2 , wherein the first and second vertical LEDs each have a maximum width of 1-100 um.

4. The display panel of claim 2 , wherein the first vertical LED is mounted to the first bottom electrode within a bank opening.

5. The display panel of claim 4 , wherein the first wavelength conversion layer completely covers the bank opening.

6. The display panel of claim 4 , further comprising a reflective bank layer within the bank opening.

7. The display panel of claim 6 , wherein the first wavelength conversion layer completely covers the bank opening.

8. The display panel of claim 6 , wherein the reflective bank layer is the first bottom electrode.

9. The display panel of claim 4 , wherein the second vertical LED is mounted to the second bottom electrode within a second bank opening.

10. The display panel of claim 9 , further comprising a second reflective bank layer within the second bank opening.

11. The display panel of claim 2 , further comprising a black matrix layer arranged between the first and second subpixels.

12. The display panel of claim 2 , wherein the phosphor particles are quantum dots.

13. The display panel of claim 12 , wherein the first wavelength conversion layer further comprises scattering particles.

14. The display panel of claim 1 , further comprising a color filter over the first wavelength conversion layer, wherein the color filter is designed to filter out light emitted from the first vertical LED.

15. The display panel of claim 1 , further comprising an array of controller chips in a pixel areas of the display substrate, each controller chip to switch and drive a corresponding plurality of vertical LEDs.

16. The display panel of claim 15 , wherein the array of controller chips includes a first controller chip to switch and drive the first and second vertical LEDs.

17. The display panel of claim 1 , wherein the first and second vertical LEDs are bonded to the first and second bottom electrodes with a solder material.

18. The display panel of claim 17 , wherein each of the first and second vertical LEDs comprises a p-n diode, and a conformal dielectric barrier layer spanning sidewalls of the p-n diode.

Assignees

• Apple Inc

Inventors

• Bibl Andreas
• Mcgroddy Kelly

Classifications

• H10W72/0198

  batch processes · CPC title

• H10W90/00 Primary

  Package configurations · CPC title

• H01L27/322

  Electricity · mapped topic

• H01L33/58

  Electricity · mapped topic

• H01L33/54

  Electricity · mapped topic