Active matrix display panel with ground tie lines

Patent metadata

Field	Value
Publication number	US-9559142-B2
Application number	US-201514931695-A
Country	US
Kind code	B2
Filing date	Nov 3, 2015
Priority date	Dec 10, 2012
Publication date	Jan 31, 2017
Grant date	Jan 31, 2017

Abstract

A display panel and a method of forming a display panel are described. The display panel may include a thin film transistor substrate including a pixel area and a non-pixel area. The pixel area includes an array of bank openings and an array of bottom electrodes within the array of bank openings. A ground line is located in the non-pixel area and an array of ground tie lines run between the bank openings in the pixel area and are electrically connected to the ground line in the non-pixel area.

First claim

What is claimed is:

1. A display panel comprising:
a display substrate including an array of ground tie lines;
a bank layer including an array of bank openings, and an array of ground tie line openings exposing the array of ground tie lines underneath the bank layer;
an array of bottom electrodes, each discrete bottom electrode spanning a bottom of a corresponding bank opening and over the bank layer;
an array of ground tie line contacts spanning a bottom of the array of ground tie line openings and over the bank layer; and
an array of vertical LED devices, each vertical LED device comprising an inorganic semiconductor-based p-n diode bonded to the bottom electrode for a corresponding bank opening.

2. The display panel of claim 1 , further comprising a sidewall passivation layer laterally around the array of vertical LED devices and filling the array of bank openings.

3. The display panel of claim 2 , further comprising a top electrode layer over and in electrical contact with the array of vertical LED devices and the array of ground tie line contacts.

4. The display panel of claim 3 , wherein the top electrode layer comprises a material selected from the group consisting of PEDOT and ITO.

5. The display panel of claim 1 , wherein the bottom electrodes are formed of a metallic film.

6. The display panel of claim 5 , wherein the ground tie lines comprise copper.

7. The display panel of claim 6 , wherein the ground tie line contacts comprise aluminum.

8. The display panel of claim 1 , wherein the array of ground tie lines includes ground tie lines running between adjacent pixels.

9. The display panel of claim 1 , wherein the array of ground tie lines includes ground tie lines running between adjacent sub-pixels.

10. The display panel of claim 1 , wherein each vertical LED device comprises a top surface that is higher than a top surface of the bank layer.

11. The display panel of claim 1 , wherein the array of ground tie lines is arranged in rows of ground tie lines, and the array of bank openings is arranged in rows of bank openings.

12. The display panel of claim 11 , wherein the rows of ground tie lines have a 1:1 correlation with the rows of bank openings.

13. The display panel of claim 11 , wherein the rows of ground tie lines have a 1:2 correlation with the rows of bank openings.

14. The display panel of claim 1 , wherein the bank openings each have a width of a few microns to 206 microns.

15. The display panel of claim 14 , wherein the bank openings each have a width of a few microns to 14 microns.

16. The display panel of claim 14 , wherein each vertical LED device has a maximum width of 1 to 100 microns.

17. The display panel of claim 16 , wherein each vertical LED device has a maximum width of 1 to 30 microns.

18. The display panel of claim 17 , wherein each vertical LED device has a maximum width of 1 to 10 microns.

Assignees

• Luxvue Tech Corp
• Apple Inc

Inventors

• Sakariya Kapil V
• Bibl Andreas
• Hu Hsin-Hua

Classifications

• H10W90/00

  Package configurations · CPC title

• H10W72/0198 Primary

  batch processes · CPC title

• G09G3/32

  semiconductive, e.g. using light-emitting diodes [LED] · CPC title

• H01L24/95

  Electricity · mapped topic

• H01L33/62

  Electricity · mapped topic