Ruthenium-based liner for a copper interconnect

Patent metadata

Field	Value
Publication number	US-12094770-B2
Application number	US-202117446398-A
Country	US
Kind code	B2
Filing date	Aug 30, 2021
Priority date	Aug 30, 2021
Publication date	Sep 17, 2024
Grant date	Sep 17, 2024

Abstract

In some implementations, one or more semiconductor processing tools may form a via within a substrate of a semiconductor device. The one or more semiconductor processing tools may deposit a ruthenium-based liner within the via. The one or more semiconductor processing tools may deposit, after depositing the ruthenium-based liner, a copper plug within the via.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, comprising:
forming a via within a substrate of the semiconductor device;
depositing a first liner comprising a first material within the via;
depositing a second liner comprising a second material on the first liner within the via;
depositing, after depositing the second liner, a plug comprising a third material within the via;
depositing a first cap comprising the second material directly on an upper surface of the plug and an upper surface of the second liner; and
depositing a second cap comprising a metal material directly on an upper surface of the first cap and on an upper surface of the first liner,
wherein the second cap is deposited to be laterally within the via.

2. The method of claim 1 , wherein the first liner is a tantalum nitride-based liner, the second liner is a ruthenium-based liner, and the plug is a copper plug.

3. The method of claim 1 , further comprising:
depositing, before depositing the plug within the via, a third liner comprising the metal material within the via,
wherein depositing the plug within the via comprises depositing the plug on the third liner.

4. The method of claim 3 , wherein depositing the first cap comprises:
depositing the first cap on an upper surface of the third liner.

5. The method of claim 3 , wherein the plug is a copper plug and the third liner is a cobalt-based liner.

6. The method of claim 1 , wherein depositing the plug within the via comprises:
depositing the third material within the via and on an upper surface of the semiconductor device, and
performing, after depositing the third material, a chemical-mechanical polishing process to remove the third material from the upper surface of the semiconductor device.

7. The method of claim 1 , further comprising:
performing, before depositing the first cap and after performing a chemical-mechanical polishing process on the upper surface of the plug, a pre-cleaning operation on an upper surface of the semiconductor device.

8. The method of claim 7 , wherein performing the pre-cleaning operation comprises application of one or more of hydrogen or ammonia plasma.

9. The method of claim 1 , further comprising:
applying, before depositing the first cap, a surfactant material to an upper surface of the substrate,
wherein the surfactant material is configured to react with the substrate to resist deposition of the second material on the upper surface of the substrate.

10. The method of claim 1 , further comprising:
applying, before depositing the first cap, one or more of methanol or a hydrogen soak to an upper surface of the substrate,
wherein the one or more of the methanol or the hydrogen soak are configured to react with the substrate to resist deposition of the second material on the upper surface of the substrate.

11. The method of claim 1 , wherein the second cap a cobalt cap and the first cap is a ruthenium cap.

12. The method of claim 1 , wherein depositing the plug comprises:
depositing the plug using a reflow deposition operation.

13. A semiconductor device, comprising:
a via within a substrate of the semiconductor device;
a first liner comprising a first material disposed within the via;
a second liner comprising a second material disposed on the first liner within the via;
a plug comprising a third material disposed on the second liner within the via;
a first cap comprising the second material disposed directly on an upper surface of the plug and an upper surface of the second liner; and
a second cap comprising a metal material disposed directly on an upper surface of the first cap and on an upper surface of the first liner,
wherein the second cap is laterally aligned with the via.

14. The semiconductor device of claim 13 , wherein the first cap is a ruthenium cap, the second cap is a cobalt cap, and the plug is a copper plug.

15. The semiconductor device of claim 13 , wherein the first liner is a tantalum nitride-based liner and the second liner is ruthenium-based liner.

16. The semiconductor device of claim 13 , wherein the second liner is a ruthenium-based liner, wherein the second material is ruthenium material and, and wherein the ruthenium-based liner further comprises cobalt material.

17. A semiconductor device, comprising:
a via within a substrate of the semiconductor device;
a first liner comprising a first material disposed within the via;
a second liner, comprising a second material and a third material, on the first liner disposed within the via;
a plug comprising a fourth material disposed on at least a portion of the second liner;
a first cap comprising the second material disposed directly on an upper surface of the plug and an upper surface of the second liner; and
a second cap comprising the third material disposed directly on an upper surface of the first cap and on an upper surface of the first liner,
wherein the second cap is laterally aligned with the first liner.

18. The semiconductor device of claim 17 , wherein the first cap is a ruthenium cap, the second cap is a cobalt cap, and the plug is a copper plug.

19. The semiconductor device of claim 17 , wherein the plug is a copper plug, the second material is ruthenium material, and the third material is cobalt material, and
wherein the copper plug is in contact with the ruthenium material and the cobalt material.

20. The semiconductor device of claim 17 , the first liner is a tantalum nitride-based liner, the second material is ruthenium material, the third material is cobalt material, and the plug is a copper plug.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Liu Yao-Min
• Gao ming-yuan
• Chiang Ming-Chou
• Chin Shu-Cheng
• Hsieh Huei-Wen
• Kuo Kai-Shiang
• Lin Yen-Chun
• Weng Cheng-Hui
• Lin Chun-Chieh
• Su Hung-Wen

Classifications

• H10P52/00

  Grinding, lapping or polishing of wafers, substrates or parts of devices · CPC title

• H10W20/425 Primary

  Barrier, adhesion or liner layers · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title