Memory system

Patent metadata

Field	Value
Publication number	US-12094541-B2
Application number	US-202117452463-A
Country	US
Kind code	B2
Filing date	Oct 27, 2021
Priority date	Sep 14, 2018
Publication date	Sep 17, 2024
Grant date	Sep 17, 2024

Abstract

According to one embodiment, a memory system includes a nonvolatile memory and a memory controller. The memory controller is configured: to store, in a buffer, a data set read from a cell unit, and an expected data set generated by an error correction on the data set; to count a number of first and second memory cells corresponding to a first and a second combination of data in the data set and the expected data set, respectively, among the memory cells in the cell unit; to calculate a shift amount of a read voltage used in a read operation from the cell unit, based on the number of the first and second memory cells; and to apply the shift amount to a next read operation from the first cell unit.

First claim

What is claimed is:

1. A controller for controlling a first nonvolatile memory including a memory cell array including a plurality of cell units each including a plurality of memory cells, the controller being configured to:
read a first data set from a first cell unit of the cell units in the first nonvolatile memory by using a first voltage and a second voltage;
read a first single state data set from the first cell unit by using a third voltage between the first voltage and the second voltage;
generate a first expected data set by an error correction on the first data set;
store, in a first buffer, the first data set, the first expected data set, and the first single state data set;
extract, from the first data set, bits corresponding to a first value of the first single state data set as a second data set;
extract, from the first expected data set, bits corresponding to the first value of the first single state data set as a second expected data set;
count a number of first memory cells corresponding to a first combination of the second data set and the second expected data set;
count a number of second memory cells corresponding to a second combination of the second data set and the second expected data set;
calculate a shift amount of the first voltage based on the counted number of the first memory cells and the counted number of the second memory cells; and
apply the shift amount to a next read operation of reading data from the first cell unit.

2. The controller of claim 1 , wherein to calculate the shift amount includes:
to calculate a ratio of the number of the second memory cells to the number of the first memory cells; and
to determine a polarity of the shift amount according to whether the ratio exceeds a reference value or not.

3. The controller of claim 2 , wherein to calculate the shift amount further includes:
to determine a magnitude of an absolute value of the shift amount in accordance with a magnitude of an absolute value of the ratio.

4. The controller of claim 1 , wherein the controller is configured:
to extract, from the first data set, bits corresponding to a second value of the first single state data set as a third data set, the second value being different from the first value;
to extract, from the first expected data set, bits corresponding to the second value of the first single state data set as a third expected data set;
to count a number of third memory cells corresponding to a third combination of the third data set and the third expected data set;
to count a number of fourth memory cells corresponding to a fourth combination of the third data set and the third expected data set; and
to calculate a shift amount of the second voltage, based on the counted number of the third memory cells and the counted number of the fourth memory cells.

5. The controller of claim 4 , wherein
the first value is a value of one of “1” and “0”, and
the second value is a value of one of “1” and “0” and is different from the first value.

6. The controller of claim 1 , wherein
each of the memory cells is capable of storing data including a first bit and a second bit,
the first data set corresponds to the first bit, and
the controller is configured:
to read a fourth data set corresponding to the second bit from the first cell unit by using a fourth voltage and a fifth voltage, the second voltage being between the third voltage and the fifth voltage, the fourth voltage being between the first voltage and the third voltage;
to generate a fourth expected data set by an error correction on the fourth data set;
to store, in the first buffer, the first data set, the first expected data set, the first single state data set, the fourth data set, and the fourth expected data set;
to extract, from the fourth data set, bits corresponding to the first value of the first single state data set as a fifth data set;
to extract, from the fourth expected data set, bits corresponding to the first value of the first single state data set as a fifth expected data set;
to count a number of fifth memory cells corresponding to an fifth combination of the second data set, the second expected data set, the fourth data set, and the fourth expected data set;
to count a number of sixth memory cells corresponding to a sixth combination of the second data set, the second expected data set, the fourth data set, and the fourth expected data set; and
to calculate a shift amount of the fourth voltage or the second voltage, based on the counted number of the fifth memory cells and the counted number of the sixth memory cells.

7. The controller of claim 6 , wherein
each of the memory cells is capable of further storing data including a third bit, and
the controller is configured to estimate a shift amount of a sixth voltage which is used in a read operation of data corresponding to the third bit, based on the calculated shift amount of the fourth voltage or the second voltage.

8. The controller of claim 1 , wherein the controller is configured:
to read the first data set from the first cell unit by using the first voltage, the second voltage, and a seventh voltage, the second voltage being between the first voltage and the seventh voltage;
to read a second single state data set from the first cell unit by using a eighth voltage between the second voltage and the seventh voltage;
to store, in the first buffer, the first data set, the first expected data set, the first single state data set, and the second single state data set;
to extract, from the first data set, bits corresponding to a second value of the first single state data set and a third value of the second single state data set as a sixth data set, the second value being different from the first value;
to extract, from the first expected data set, bits corresponding to the second value of the first single state data set and the third value of the second single state data set as a sixth expected data set;
to count a number of seventh memory cells corresponding to a seventh combination of the sixth data set and the sixth expected data set;
to count a number of eighth memory cells corresponding to a eighth combination of the sixth data set and the sixth expected data set; and
to calculate a shift amount of the second voltage, based on the counted number of the seventh memory cells and the counted number of the eighth memory cells.

9. The controller of claim 1 , wherein
the controller is configured to control a second nonvolatile memory including a memory cell array which includes a plurality of cell units each including a plurality of memory cells, and
the controller is configured:
to read a seventh data set from a second cell unit of the cell units in the second nonvolatile memory by using the first voltage and the second voltage;
to read a third single state data set from the second cell unit by using the third voltage;
to generate seventh first expected data set by an error correction on the seventh data set;
to store, in a second buffer, the seventh data set, the seventh expected data set, and the third single state data set;
to extract, from the second data set, bits corresponding to the first value of the third single state data set as an eighth data set;
to extract, from the first expected data set, bits corresponding to the first value of the third single state data set as an eighth expected data set;
to count a number of ninth memory cells corresponding to a ninth combination of the eighth data set and the eighth expected data set;
to count a number of tenth memory cells corresponding to a tenth combination of the eighth data set and the eighth expected data set;
to calculate a shift amount of the first voltage based on th

Assignees

• Kioxia Corp

Inventors

• Tokutomi Tsukasa
• Shirakawa Masanobu
• Kurose Kengo
• Takada Marie
• Yamaki Ryo
• Iwasaki Kiyotaka
• Kojima Yoshihisa

Classifications

• H10B43/35

  with cell select transistors, e.g. NAND · CPC title

• H10B43/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title