Reduced level cell mode for non-volatile memory

Patent metadata

Field	Value
Publication number	US-9595318-B2
Application number	US-201514984491-A
Country	US
Kind code	B2
Filing date	Dec 30, 2015
Priority date	Mar 15, 2010
Publication date	Mar 14, 2017
Grant date	Mar 14, 2017

Abstract

Apparatuses, systems, methods, and computer program products are disclosed for reduced level cell solid-state storage. A method includes determining that an erase block of a non-volatile storage device is to operate in a reduced level cell (RLC) mode. The non-volatile storage device may be configured to store at least three bits of data per storage cell. A method includes instructing the non-volatile storage device to program first and second pages of the erase block with data. A method includes instructing the non-volatile storage device to program a third page of the erase block with a predefined data pattern. Programming of a predefined data pattern may be configured to adjust which abodes of the erase block are available to represent stored user data values.

First claim

What is claimed is:

1. A method comprising:
determining that a set of storage cells of a non-volatile storage device is to operate in a reduced level cell (RLC) mode, wherein storage cells of the set of storage cells are configured to store at least two bits of data per storage cell;
instructing the non-volatile storage device to program a first page of the set of storage cells with data; and
instructing the non-volatile storage device to program a second page of the set of storage cells with a predefined data pattern, the programming of the predefined data pattern configured to adjust which abodes of the set of storage cells are available to represent stored user data values.

2. The method of claim 1 , further comprising performing an operation on the data of the first page, wherein results of the operation comprise the predefined data pattern for the second page.

3. The method of claim 2 , wherein the operation comprises an XNOR logical equality operation.

4. The method of claim 2 , further comprising buffering the data of the first page prior to programming the first page of the set of storage cells, the operation performed on the buffered data.

5. The method of claim 4 , wherein the data of the first page is buffered in one or more different sets of storage cells of the non-volatile storage device such that the data of the first page may be programmed to the one or more different sets of storage cells after a restart event for the non-volatile storage device.

6. The method of claim 1 , further comprising adjusting, for the RLC mode, one or more thresholds for the abodes of the set of storage cells to provide one or more separation distances between the available abodes.

7. The method of claim 6 , wherein the one or more thresholds are set to merge at least one of the available abodes with at least one abode unavailable to represent stored user data to provide the one or more separation distances.

8. The method of claim 6 , wherein the one or more thresholds are set to move adjacent available abodes away from each other to provide the one or more separation distances.

9. The method of claim 1 , further comprising maintaining a page of data in a different set of storage cells of the non-volatile storage device, the page of data comprising the predefined data pattern for programming the second page.

10. The method of claim 1 , wherein the predefined data pattern comprises error correction information for the data of the first page.

11. The method of claim 1 , wherein up to half of the abodes of the set of storage cells are available to represent stored user data in the RLC mode.

12. An apparatus comprising:
a trigger module that determines whether an error rate for a set of non-volatile memory cells satisfies an error threshold;
a program module that writes workload data to one or more lower pages of the set of non-volatile memory cells with each memory cell representing at least two bits of data by way of one of a set of program states; and
an endurance module that writes an endurance data pattern to an upper page of the set of non-volatile memory cells instead of workload data to the upper page in response to the error rate satisfying the error threshold, thereby defining a subset of the program states of the set of non-volatile memory cells for encoding workload data;
wherein at least a portion of the trigger module, the program module, and the endurance module comprises one or more of hardware and executable code, the executable code being stored on one or more computer readable storage media.

13. The apparatus of claim 12 , further comprising a threshold module that adjusts one or more thresholds for the program states of the set of non-volatile memory cells in response to the error rate satisfying the error threshold to provide one or more separation distances between the subset of the program states selected for encoding workload data.

14. The apparatus of claim 12 , further comprising a pattern module that determines the endurance pattern based on the workload data for the one or more lower pages.

15. The apparatus of claim 12 , further comprising a retirement module that retires the set of non-volatile memory cells from storing workload data in response to the error rate satisfying a retirement error threshold.

16. The apparatus of claim 12 , wherein the program module writes workload data to the upper page of the set of non-volatile memory cells in response to the error rate failing to satisfy the error threshold.

17. The apparatus of claim 12 , wherein the endurance data pattern is selected for use in defining subsets of program states for different architectures of non-volatile memory cells, the different architectures comprising different arrangements of program states for a predefined data encoding for the program states of the non-volatile memory cells.

18. An apparatus comprising:
means for monitoring an error rate for a region of non-volatile recording cells, each recording cell of the non-volatile recording cells encoding at least two bits of data using a set of abodes;
means for directing user data to be programmed to recording cells of the region of non-volatile recording cells for at least one bit of the at least two bits of data; and
means for adjusting one or more thresholds for the abodes of the recording cells in response to the error rate satisfying an error threshold to provide one or more separation distances between a subset of the abodes available for encoding the at least one bit of the at least two bits of data;
wherein at least a portion of the means for monitoring the error rate, the means for directing the user data, and the means for adjusting the one or more thresholds comprises one or more of hardware and executable code, the executable code being stored on one or more computer readable storage media.

19. The apparatus of claim 18 , further comprising means for directing a data pattern to be programmed to the second bit of the at least two bits of data, the programming of the data pattern determining which subset of the abodes is available for encoding the at least one bit of the at least two bits of data.

20. The apparatus of claim 18 , wherein the second bit of the at least two bits of data is unprogrammed in response to the error rate satisfying the error threshold.

Assignees

• Longitude Entpr Flash S A R L
• Sandisk Technologies Llc

Inventors

• Hyun Jea
• Haynes Ryan
• Mosier Charla
• Lucky Rick
• Wood Robert

Classifications

• G06F11/1072

  in multilevel memories · CPC title

• G06F2212/7207

  management of metadata or control data · CPC title

• G11C11/5642

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C11/5628

  Programming or writing circuits; Data input circuits · CPC title