Shared data fabric processing client reset system and method

Patent metadata

Field	Value
Publication number	US-12093689-B2
Application number	US-202017032301-A
Country	US
Kind code	B2
Filing date	Sep 25, 2020
Priority date	Sep 25, 2020
Publication date	Sep 17, 2024
Grant date	Sep 17, 2024

Abstract

A processing system that includes a shared data fabric resets a first client processor while operating a second client processor. The first client processor is instructed to stop making requests to one or more devices of the shared data fabric. Status communications are blocked between the first client processor and a memory controller, the second client processor, or both, such that the first client processor enters a temporary offline state. The first client processor is indicated as being non-coherent. Accordingly, when the processor is reset some errors and efficiency losses due messages sent during or prior to the reset are prevented.

First claim

What is claimed is:

1. A method comprising:
based on a reset of a first client processor of a shared data fabric processing system and without resetting a second client processor of the shared data fabric processing system:
instructing the first client processor to stop making requests to one or more devices of the shared data fabric processing system;
blocking status communications between the first client processor and a memory controller of the shared data fabric processing system; and
causing the first client processor to reset; and

reenabling the first client processor.

2. The method of claim 1 , further comprising stopping, by the first client processor, the requests to the one or more devices of the shared data fabric processing system by terminating chained write operations and completing write operations.

3. The method of claim 1 , further comprising:
subsequent to blocking the status communications, indicating that the first client processor is non-coherent to the memory controller.

4. The method of claim 3 , wherein reenabling the first client processor comprises:
allowing the status communications between the first client processor and the memory controller to resume; and
indicating that the first client processor is coherent to the memory controller.

5. The method of claim 4 ,
wherein blocking the status communications causes the first client processor to enter a temporary offline state, and
wherein allowing the status communications to resume causes the first client processor to exit the temporary offline state.

6. The method of claim 5 , further comprising:
subsequent to the first client processor entering the temporary offline state and prior to indicating that the first client processor is non-coherent, waiting for remaining status requests to the first client processor to be answered.

7. The method of claim 4 ,
wherein blocking the status communications comprises disabling flow control checks on status responses by the first client processor, and
wherein allowing the status communications to resume comprises enabling flow control checks on status responses by the first client processor.

8. The method of claim 4 ,
wherein blocking the status communications comprises enabling a spoofing of probes sent to the first client processor, and
wherein allowing the status communications to resume comprises disabling the spoofing of probes sent to the first client processor.

9. The method of claim 8 , wherein enabling the spoofing of probes comprises sending, by a coherent agent associated with the first client processor, a spoofed probe response generated in response to a probe addressed to the first client processor.

10. The method of claim 9 , wherein enabling the spoofing of probes comprises generating, by a coherent agent associated with the first client processor, the spoofed probe response.

11. The method of claim 1 , further comprising instructing a coherent agent associated with the first client processor to treat the first client processor as having a fused off state in a data fabric of the shared data fabric processing system.

12. An integrated circuit (IC) comprising:
a parallel processing unit;
a central processing unit (CPU); and
a data fabric comprising:
a memory controller configured to:
send status communications from the CPU to the parallel processing unit,
wherein the status communications comprise packets and probes; and

a coherent agent configured to:
reset the parallel processing unit without resetting the CPU;
in response to the reset of the parallel processing unit, block the status communications between the memory controller and the parallel processing unit; and
triggering a reset of the parallel processing unit.

13. The IC of claim 12 , wherein the memory controller is further configured to:
mark the parallel processing unit as non-coherent subsequent to status communications between the memory controller and the parallel processing unit being blocked for at least a particular amount of time.

14. The IC of claim 12 , wherein the coherent agent comprises a credit counter configured to select between a first number of processing credits indicated by a credit availability signal from the parallel processing unit and zero processing credits based on a credit reset signal, and wherein the credit reset signal is sent as part of blocking the status communications between the memory controller and the parallel processing unit.

15. The IC of claim 14 , wherein the coherent agent comprises a selection module configured to instruct, based on an indication of processing credits of the parallel processing unit received from the credit counter, one or more memory devices of the coherent agent to send status communications to the parallel processing unit.

16. The IC of claim 12 , wherein the coherent agent comprises a spoof module configured to send a spoofed probe response to the memory controller as part of blocking the status communications between the memory controller and the parallel processing unit.

17. A method comprising:
based on a reset of a first client processor of a processing system that comprises at least one graphic processing unit (GPU) and at least one central processing unit (CPU) and without resetting a second client processor of the processing system:
intercepting status communications between the first client processor and a memory controller of a data fabric of the processing system; and
instructing the first client processor to reset; and

reenabling the first client processor.

18. The method of claim 17 , wherein processing credits of the first client processor are distributed to one or more devices connected to the data fabric, and wherein intercepting the status communications comprises:
wiping the processing credits of the first client processor; and
resetting the processing credits of the first client processor to an initial credit count.

19. The method of claim 17 , further comprising:
instructing the first client processor to stop making requests to one or more devices connected to a data fabric of the processing system; and
preventing processing credits of a second client processor from being allocated to the first client processor.

20. The method of claim 17 , wherein intercepting the status communications comprises disabling flow control checks on responses by the first client processor.

Assignees

• Advanced Micro Devices Inc
• Ati Technologies Ulc

Inventors

• Tsien Benjamin
• Branover Alexander J
• Petry John
• Yang Chen-Ping
• Kyrychynskyi Rostyslav
• Kalyanasundharam Vydhyanathan

Classifications

• G06F9/3005 Primary

  to perform operations for flow control · CPC title

• G06F9/3877

  using a secondary processor, e.g. coprocessor (peripheral processor G06F13/12) · CPC title

• G06F9/463

  Program control block organisation · CPC title

• G06F13/4022 Primary

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

• G06F2212/1052

  Security improvement · CPC title