Virtual legacy wire

Patent metadata

Field	Value
Publication number	US-2016188503-A1
Application number	US-201414583154-A
Country	US
Kind code	A1
Filing date	Dec 25, 2014
Priority date	Dec 25, 2014
Publication date	Jun 30, 2016
Grant date	—

Abstract

In an example, a system on chip (SoC) includes virtual legacy wire (VLW) functionality. The VLW signal virtualizes a physical interrupt existing in legacy systems to enable a peripheral to cause a processor to enter an interrupt handling routine relevant to the peripheral. The VLW interrupt is broadcast to all cores or agents within the SoC. However, to save power, if one or more agents are asleep when the interrupt occurs, the agents are not awakened to receive the interrupt. Rather, the VLW is broadcast with a mask to exclude those agents, and the state of those agents is stored in a register or buffer. Once a power management agent notifies the VLW broadcaster that an agent has newly awakened. The VLW interrupt is then re-broadcast, with a mask that excludes all but the newly-awakened agent.

First claim

What is claimed is:

1 . An apparatus comprising:
a virtual legacy interrupt receiver to receive a virtual legacy interrupt signal from a peripheral device; a power management interface to receive a signal to identify out-of-service agents; and a virtual legacy wire broadcaster to broadcast a virtual legacy wire interrupt on a bus with a mask to exclude the out-of-service agents.

2 . The apparatus of claim 1 , wherein the signal to identify out-of-service agents is to identify agents that are asleep.

3 . The apparatus of claim 1 , further comprising a state manager to cause the identities of the out-of-service agents to be stored.

4 . The apparatus of claim 3 , wherein the state manager is to cause the identities of the out-of-service agents to be stored in a register.

5 . The apparatus of claim 3 , wherein the state manager is to cause the identities of the out-of-service agents to be stored in a buffer.

6 . The apparatus of claim 1 , wherein:
the power management interface is further to receive a signal to identify an agent that has awakened; and the virtual legacy wire broadcaster is further to broadcast a virtual legacy wire interrupt on the bus with a mask to exclude all but the agent that has awakened.

7 . The apparatus of claim 1 , further comprising logic to determine that all agents have been serviced with the virtual legacy wire interrupt, and to terminate the virtual legacy wire interrupt.

8 . A system on chip, comprising:
a plurality of agents; a power management agent to detect that one or more agents are out of service; a peripheral interface; and a virtual legacy interrupt handler, comprising
a virtual legacy interrupt receiver to receive a virtual legacy interrupt signal via the peripheral interface;
a power management interface to receive a signal from the power management agent to identify zero or more out-of-service agents; and
a virtual legacy wire broadcaster to broadcast a virtual legacy wire interrupt on a bus with a mask to exclude the out-of-service agents.

9 . The system on chip of claim 8 , wherein the signal to identify out-of-service agents is to identify agents that are asleep.

10 . The system on chip of claim 8 , further comprising a state manager to cause the identities of the out-of-service agents to be stored.

11 . The system on chip of claim 10 , further comprising a state register, wherein the state manager is to cause the identities of the out-of-service agents to be stored in the state register.

12 . The system on chip of claim 10 , further comprising a state buffer, wherein the state manager is to cause the identities of the out-of-service agents to be stored in the state buffer.

13 . The system on chip of claim 8 , wherein:
the power management interface is further to receive a signal from the power management agent to identify an agent that has awakened; and the virtual legacy wire broadcaster is further to broadcast a virtual legacy wire interrupt on the bus with a mask to exclude all but the agent that has awakened.

14 . The system on chip of claim 8 , further comprising logic to determine that all agents have been serviced with the virtual legacy wire interrupt, and to terminate the virtual legacy wire interrupt.

15 . At least one machine accessible storage medium having code stored thereon, the code when executed on a machine, causes the machine to:
receive a virtual legacy interrupt signal from a peripheral device; receive a signal to identify out-of-service agents; and broadcast a virtual legacy wire interrupt on a bus with a mask to exclude the out-of-service agents.

16 . The storage medium of claim 15 , wherein identifying out-of-service agents comprises identifying agents that are asleep.

17 . The storage medium of claim 15 , wherein the code, when executed, further causes the machine to store the identity of the out-of-service agents.

18 . The storage medium of claim 17 , wherein storing the identity of the out-of-service agents comprises storing the identity in a state register.

19 . The storage medium of claim 17 , wherein storing the identity of the out-of-service agents comprises storing the identity in a state register.

20 . The storage medium of claim 15 , wherein the code, when executed, further causes the machine to:
identify an agent that has awakened; and broadcast a virtual legacy wire interrupt on the bus with a mask to exclude all but the agent that has awakened.

Assignees

• Intel Corp

Inventors

• Hallnor Erik G

Classifications

• G06F13/24 Primary

  using interrupt (G06F13/32 takes precedence) · CPC title

• G06F13/426

  using an embedded synchronisation, e.g. Firewire bus, Fibre Channel bus, SSA bus · CPC title

• G06F9/4418

  Suspend and resume; Hibernate and awake · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title