Caching policies for processing units on multiple sockets

Patent metadata

Field	Value
Publication number	US-10467138-B2
Application number	US-201514981833-A
Country	US
Kind code	B2
Filing date	Dec 28, 2015
Priority date	Dec 28, 2015
Publication date	Nov 5, 2019
Grant date	Nov 5, 2019

Abstract

A processing system includes a first socket, a second socket, and an interface between the first socket and the second socket. A first memory is associated with the first socket and a second memory is associated with the second socket. The processing system also includes a controller for the first memory. The controller is to receive a first request for a first memory transaction with the second memory and perform the first memory transaction along a path that includes the interface and bypasses at least one second cache associated with the second memory.

First claim

What is claimed is:

1. A method comprising:
receiving, at a first controller for a first memory directly associated with a first socket, a first request for a first memory transaction with a second memory, distinct from the first memory, directly associated with a second socket, distinct from the first socket, connected to the first socket by an interface; and
performing the first memory transaction along a path that includes the interface and bypasses at least one second cache directly associated with the second memory.

2. The method of claim 1 , wherein the first socket includes at least one first central processing unit (CPU) and at least one first graphics processing unit (GPU), and wherein the second socket includes at least one second CPU and at least one second GPU, and wherein receiving the first request for the first memory transaction comprises receiving the first request for the first memory transaction from the at least one first GPU.

3. The method of claim 1 , wherein receiving the first request for the first memory transaction comprises receiving the first request for the first memory transaction from a network interface card connected to the first socket.

4. The method of claim 1 , further comprising:
invalidating at least one cache line in at least one first cache directly associated with the first socket in response to the first request for the first memory transaction and based on the path selected for the first request.

5. The method of claim 4 , wherein cache lines in at least one second cache directly associated with the second socket are not invalidated by cache probes transmitted over the interface in response to the first request for the first memory transaction with the second memory.

6. The method of claim 5 , wherein a second controller directly associated with the second socket transmits at least one cache probe to invalidate cache lines in at least one second cache directly associated with the second socket and bypasses transmitting cache probes over the interface.

7. The method of claim 6 , further comprising:
receiving, at the first controller, a second request for a second memory transaction with the first memory; and
bypassing transmission of a cache probe over the interface to the at least one second cache in response to receiving the second request.

8. The method of claim 7 , further comprising:
invalidating at least one line in at least one first cache directly associated with the first memory based on a virtual address directly associated with the second memory transaction.

9. An apparatus comprising:
a first socket and a second socket distinct from the first socket;
an interface between the first socket and the second socket;
a first memory directly associated with the first socket and a second memory distinct from the first memory and directly associated with the second socket; and
a first controller for the first memory, wherein the first controller is to receive a first request for a first memory transaction with the second memory and perform the first memory transaction along a path that includes the interface and bypasses at least one second cache directly associated with the second memory.

10. The apparatus of claim 9 , further comprising:
at least one first central processing unit (CPU) and at least one first graphics processing unit (GPU) implemented on the first socket; and
at least one second CPU and at least one second GPU implemented on the second socket, wherein the first controller is to receive the first request for the first memory transaction from the at least one first GPU.

11. The apparatus of claim 9 , further comprising:
a network interface card connected to the first socket, and wherein the first controller is to receive the first request for the first memory transaction from the network interface card.

12. The apparatus of claim 9 , further comprising:
at least one first cache directly associated with the first socket, and wherein the first controller is to invalidate at least one cache line in the at least one first cache in response to the first request for the first memory transaction.

13. The apparatus of claim 12 , further comprising:
at least one second cache directly associated with the second socket, wherein cache lines in the at least one second cache are not invalidated by cache probes transmitted over the interface in response to the first request for the first memory transaction with the second memory.

14. The apparatus of claim 13 , further comprising:
a second controller directly associated with the second socket, wherein the second controller transmits at least one cache probe to invalidate cache lines in at least one second cache directly associated with the second socket and bypasses transmitting cache probes over the interface.

15. The apparatus of claim 14 , wherein the first controller is to receive a second request for a second memory transaction with the first memory and bypass transmission of a cache probe over the interface to the at least one second cache in response to receiving the second request.

16. The apparatus of claim 15 , where the first controller is to invalidate at least one line in at least one first cache directly associated with the first memory based on a virtual address directly associated with the second memory transaction.

17. A non-transitory computer readable storage medium embodying a set of executable instructions, the set of executable instructions to manipulate a computer system to perform a portion of a process to fabricate at least part of a processing system, the processing system comprising:
a first socket and a second socket distinct from the first socket;
an interface between the first socket and the second socket;
a first memory directly associated with the first socket and a second memory distinct from the first memory and directly associated with the second socket; and
a first controller for the first memory, wherein the first controller is to receive a first request for a first memory transaction with the second memory and perform the first memory transaction along a path that includes the interface and bypasses at least one second cache directly associated with the second memory.

18. The non-transitory computer readable storage medium of claim 17 , wherein the processing system further comprises:
a network interface card connected to the first socket, and wherein the first controller is to receive the first request for the first memory transaction from the network interface card.

19. The non-transitory computer readable storage medium of claim 17 , wherein the processing system further comprises:
at least one first cache directly associated with the first socket, and wherein the first controller is to invalidate at least one cache line in the at least one first cache in response to the first request for the first memory transaction; and
at least one second cache directly associated with the second socket, wherein cache lines in the at least one second cache are not invalidated by cache probes transmitted over the interface in response to the first request for the first memory transaction with the second memory.

20. The non-transitory computer readable storage medium of claim 19 , wherein the processing system further comprises:
a second controller directly associated with the second socket, wherein the second controller transmits at least one cache probe to invalidate cache lines in at least one second cache directly associated with the second socket and bypasses tra

Assignees

• Advanced Micro Devices Inc

Inventors

• Blinzer Paul
• Ibrahim Ali
• Sander Benjamin T
• Kalyanasundharam Vydhyanathan

Classifications

• G06F12/0813

  with a network or matrix configuration · CPC title

• G06F2212/154

  Networked environment · CPC title

• G06F2212/621

  Coherency control relating to peripheral accessing, e.g. from DMA or I/O device · CPC title

• G06F12/0815 Primary

  Cache consistency protocols · CPC title

• G06F12/0888

  using selective caching, e.g. bypass · CPC title