Memory circuit and cache circuit configuration

Patent metadata

Field	Value
Publication number	US-12093176-B2
Application number	US-202318341088-A
Country	US
Kind code	B2
Filing date	Jun 26, 2023
Priority date	Nov 2, 2012
Publication date	Sep 17, 2024
Grant date	Sep 17, 2024

Abstract

A memory system includes multiple groups of primary memory cells residing in a first die or a stack of first dies, multiple groups of cache memory cells residing in a second die, an interposer, and control circuits residing in a third die. Each group of the cache memory cells is associated with a corresponding group of the primary memory cells. The first die or the stack of first dies is coupled to a top surface of the second die through a first group of bumps. A bottom surface of the second die is coupled to a top surface of the interposer through a second group of bumps. The control circuits are associated with the primary memory cells and the cache memory cells. The third die is positioned aside the second die and coupled to the top surface of the interposer through a third group of pumps.

First claim

What is claimed is:

1. A memory system, comprising:
multiple groups of primary memory cells residing in a first die or a stack of first dies;
multiple groups of cache memory cells residing in a second die, wherein each group of the cache memory cells is associated with a corresponding group of the primary memory cells, and wherein the first die or the stack of first dies is coupled to a top surface of the second die through a first group of bumps;
an interposer, wherein a bottom surface of the second die is coupled to a top surface of the interposer through a second group of bumps; and
control circuits residing in a third die, wherein the control circuits are associated with the primary memory cells and the cache memory cells, and wherein the third die is positioned aside the second die and coupled to the top surface of the interposer through a third group of pumps.

2. The memory system of claim 1 , wherein the control circuits include a first control circuit coupled to the primary memory cells and a second control circuit coupled to the cache memory cells.

3. The memory system of claim 2 , wherein the first control circuit also couples to the cache memory cells.

4. The memory system of claim 1 , wherein the primary memory cells operate at a speed slower than the cache memory cells.

5. The memory system of claim 1 , wherein the primary memory cells are dynamic random-access memory (DRAM) cells, and the cache memory cells are static random-access memory (SRAM) cells.

6. The memory system of claim 1 , wherein the second group of bumps outnumbers the first group of bumps.

7. The memory system of claim 6 , wherein the second group of bumps includes a first portion being pin-to-pin compatible with the first group of bumps and a second portion not corresponding to the first group of bumps.

8. The memory system of claim 7 , wherein, in a top view of the second die, the first portion of the second group of bumps occupies a first strip region and the second portion of the second group of bumps occupies second and third strip regions that sandwich the first strip region.

9. The memory system of claim 7 , wherein the first group of bumps is electrically coupled to the first portion of the second group of bumps by vias traveling through the second die.

10. The memory system of claim 1 , further comprising:
a group of first memory cells residing in the second die and associated with addresses of data stored in the cache memory cells; and
a group of second memory cells residing in the second die and associated with validity of data stored in the cache memory cells.

11. A memory system, comprising:
a first die including a first memory circuit;
a second die including a second memory circuit, the first and second memory circuits being of different types, the first and second memory circuits being coupled to each other; and
a third die including a memory controller circuit and a cache controller circuit, the memory controller circuit coupled to the first memory circuit and the second memory circuit, and the cache controller circuit coupled to the second memory circuit and the memory controller circuit.

12. The memory system of claim 11 , wherein the first memory circuit operates slower than the second memory circuit.

13. The memory system of claim 11 , wherein the cache controller circuit is free of direct coupling with the first memory circuit.

14. The memory system of claim 11 , wherein the cache controller circuit is operable to read data from the second memory circuit without operating the memory controller circuit.

15. The memory system of claim 11 , further comprising:
a bus carrying read/write commands, wherein the bus is coupled to both the cache controller circuit and the memory controller circuit.

16. The memory system of claim 11 , wherein the first memory circuit has P access channels of Q bits of channel bandwidth, and wherein the second memory circuit includes P subsets of Q*N memory cells, P and Q being integers greater than 1, N being a positive integer.

17. The memory system of claim 16 , wherein the second die is operable to store a duplication of n*P*Q bits of consecutively addressed data from the first memory circuit to the second memory circuit, n being an integer from 1 to N and being dynamically set.

18. A memory system, comprising:
a primary memory circuit formed of a first die or a set of stacked dies, the primary memory circuit comprising P sets of primary memory cells, each set of the primary memory cells having Q input/output (I/O) terminals, P and Q being integers greater than 1;
a cache memory circuit formed of a second die, the cache memory circuit comprising D sets of cache memory cells, and each set of the cache memory cells comprising P subsets of Q*N cache memory cells, each of the P subsets of the cache memory cells associated with a corresponding one of the P sets of primary memory cells, D and N being positive integers;
a memory controller circuit electrically coupled with the primary memory circuit, the memory controller circuit being configured to access the P sets of primary memory cells; and
a cache controller circuit electrically coupled with the memory controller circuit and the cache memory circuit, the cache controller circuit being configured to receive a read command for reading requested data stored in the primary memory circuit at a read address and to retrieve a valid duplication of the requested data from the cache memory circuit if the valid duplication of the requested data exists in the cache memory circuit,
wherein the valid duplication of the requested data occupies n*P*Q cache memory cells in the cache memory circuit, n being an integer from 1 to N and being dynamically set.

19. The memory system of claim 18 , wherein n is dynamically set according to how often a pre-fetch data is used or additional cycles available between two read/write commands.

20. The memory system of claim 18 , wherein the first die or the set of stacked dies is stacked on the second die, and wherein the memory controller circuit and the cache controller circuit are formed of a third die.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lee Hsien-Hsin Sean
• Shen William Wu
• Lee Yun-Han

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• G11C7/22

  Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management · CPC title

• G06F2212/608

  Details relating to cache mapping · CPC title

• G06F2212/45

  Caching of specific data in cache memory · CPC title

• G06F2212/1032

  Reliability improvement, data loss prevention, degraded operation etc · CPC title