Tap dual port router with update lead and gated updatedr

Patent metadata

Field	Value
Publication number	US-10197626-B2
Application number	US-201715652911-A
Country	US
Kind code	B2
Filing date	Jul 18, 2017
Priority date	Aug 17, 2011
Publication date	Feb 5, 2019
Grant date	Feb 5, 2019

Abstract

This disclosure describes a test architecture that supports a common approach to testing individual die and dies in a 3D stack arrangement. The test architecture uses an improved TAP design to facilitate the testing of parallel test circuits within the die.

First claim

What is claimed is:

1. An integrated circuit comprising:
(a) a test data in lead, a test clock lead, a test mode select lead, a test data out lead, and an update lead;
(b) a TAP state machine having a clock input coupled to the test clock lead, a mode input coupled to the test mode select lead, data register control outputs that include a ClockDR signal and an UpdateDR signal, and instruction register control outputs;
(c) an instruction register having a test data input coupled to the test data in lead, instruction register control inputs coupled to the instruction register control outputs, and instruction register outputs;
(d) data registers having test data inputs coupled to the test data in lead, data register control inputs, and instruction register control inputs coupled to the instruction register outputs; and
(e) dual port router circuitry having:
(i) first multiplexer circuitry having an input connected to the update lead, an input connected to the UpdateDR signal, a control input connected to one of the instruction register outputs, and an output;
(ii) first gating circuitry having an input connected to the output of the multiplexer circuitry, an input connected to the control input of the first multiplexer circuitry, and a gated UpdateDR signal output coupled to a data register control input of the data registers.

2. The integrated circuit of claim 1 in which each of the instruction register and the data registers have a test data output, and including a second multiplexer having an input for each test data output, and an output coupled to the test data out lead.

3. The integrated circuit of claim 1 in which each of the instruction register and the data registers have a test data output, and the state machine has a select output, and including a second multiplexer having a select input coupled to the select output, instruction register inputs coupled to the instruction register outputs, an input for each test data output, and an output coupled to the test data out lead.

4. The integrated circuit of claim 1 in which the dual port router circuitry includes second gating circuitry having an input connected to the ClockDR signal, an input connected to the control input of the first multiplexer circuitry, and a gated ClockDR signal output coupled to a data register control input of the data registers.

Assignees

• Texas Instruments Inc

Inventors

• Whetsel Lee D

Classifications

• G01R31/31725

  Timing aspects, e.g. clock distribution, skew, propagation delay (for tester hardware G01R31/31937) · CPC title

• G01R31/318597

  JTAG or boundary scan test of memory devices (other scan testing of memories G11C29/32) · CPC title

• G01R31/318513

  Test of Multi-Chip-Moduls · CPC title

• G01R31/318555 Primary

  Control logic · CPC title

• G01R31/31724

  Test controller, e.g. BIST state machine (for scan test G01R31/318555) · CPC title