Semiconductor memory

Patent metadata

Field	Value
Publication number	US-12089409-B2
Application number	US-202318339526-A
Country	US
Kind code	B2
Filing date	Jun 22, 2023
Priority date	Sep 19, 2017
Publication date	Sep 10, 2024
Grant date	Sep 10, 2024

Abstract

According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip comprises first conductors stacked via an insulator, and a first pillar passing the first conductors. The circuit chip comprises a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode comprises a portion extending from a side of the surface of the first memory chip through the first memory chip and connected to the second conductor. Part of the first conductors is between the external connection electrode and the substrate.

First claim

The invention claimed is:

1. A semiconductor memory comprising:
a memory chip comprising a first area, a second area, and a third area provided in this order in a first direction,
the first area comprising a first memory cell array that comprises first memory cells, a first bit line, and a first word line,
the second area not comprising a memory cell array,
the third area comprising a second memory cell array that comprises second memory cells, a second bit line, and a second word line; and

a circuit chip attached to the memory chip and comprising a fourth area, a fifth area, and a sixth area provided in this order in the first direction,
the fourth area comprising a first sense amplifier electrically connected to one of the first memory cells via the first bit line,
the fifth area not comprising a sense amplifier,
the sixth area comprising a second sense amplifier electrically connected to one of the second memory cells via the second bit line;

wherein the first area and the fourth area overlap in a second direction crossing the first direction, and
the third area and the sixth area overlap in the second direction.

2. The semiconductor memory of claim 1 , wherein
the first word line is more than one,
the first memory cell array further comprises a first stack of said more than one first word line and a first pillar extending through the first stack, each of intersections between the first pillar and said more than one first word line being configured as the first memory cell,
the second word line is more than one,
the second memory cell array further comprises a second stack of said more than one second word line and a second pillar extending through the second stack, each of intersections between the second pillar and said more than one second word line being configured as the second memory cell,
the circuit chip comprises a substrate on which the first and second sense amplifiers are located,
part of the first bit line is between the substrate and said more than one first word line, and
part of the second bit line is between the substrate and said more than one second word line.

3. The semiconductor memory of claim 2 , wherein
the first memory cell array further comprises a first source line above the first stack, the first pillar comprising an upper portion contacting the first source line, and
the second memory cell array further comprises a second source line above the second stack, the second pillar comprising an upper portion contacting the second source line.

4. The semiconductor memory of claim 1 , wherein
the circuit chip further comprises a seventh area next to the fourth area in a third direction crossing the first and second directions, the seventh area comprising a control circuit configured to control the first memory cell array, and
the first area and the seventh area overlap in the second direction.

5. The semiconductor memory of claim 4 , wherein
the seventh area is next to the fifth area in the first direction.

6. The semiconductor memory of claim 1 , wherein
the memory chip further comprises a eighth area next to the first area and the second area in a third direction crossing the first and second directions, and
the circuit chip further comprises a ninth area overlapping the eighth area in the second direction and comprising an input/output circuit.

7. The semiconductor memory of claim 6 , further comprising:
a pad on the memory chip, the pad being electrically connected to the input/output circuit and overlapping the first area and the eighth area in the second direction.

Assignees

• Kioxia Corp

Inventors

• Tagami Masayoshi
• Iijima Jun
• Katsumata Ryota
• Higashi Kazuyuki

Classifications

• H10W90/792

  between multiple chips · CPC title

• H10W80/333

  Compression bonding · CPC title

• H10W80/312

  characterised by the direct bonding of electrically conductive pads · CPC title

• H10W80/301

  Bonding techniques, e.g. hybrid bonding · CPC title

• H10W72/9232

  with additional elements interposed between layers · CPC title