Die seal ring for integrated circuit system with stacked device wafers
US-9142581-B2 · Sep 22, 2015 · US
Die seal ring for integrated circuit system with stacked device wafers
US9305968B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9305968-B2 |
| Application number | US-201514825703-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 13, 2015 |
| Priority date | Nov 5, 2012 |
| Publication date | Apr 5, 2016 |
| Grant date | Apr 5, 2016 |
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Abstract
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An integrated circuit system includes a first device wafer bonded to a second device wafer at a bonding interface of dielectrics. Each wafer includes a plurality of dies, where each die includes a device, a metal stack, and a seal ring that is formed at an edge region of the die. Seal rings included in dies of the second device wafer each include a first conductive path provided with metal formed in a first opening that extends from a backside of the second device wafer, through the second device wafer, and through the bonding interface to the seal ring of a corresponding die in the first device wafer.
First claim
Opening claim text (preview).
What is claimed is: 1. A method of fabricating an integrated circuit system, the method comprising: providing a first die including: a first device formed in an integrated circuit region of a first semiconductor layer, and a first metal stack formed on the first semiconductor layer, the first metal stack including one or more metal layers formed in a dielectric layer; providing a second die including: a second device formed in an integrated circuit region of a second semic…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US9305968B2 cover?
- An integrated circuit system includes a first device wafer bonded to a second device wafer at a bonding interface of dielectrics. Each wafer includes a plurality of dies, where each die includes a device, a metal stack, and a seal ring that is formed at an edge region of the die. Seal rings included in dies of the second device wafer each include a first conductive path provided with metal form…
- Who is the assignee on this patent?
- Omnivision Tech Inc
- What technology area does this patent fall under?
- Primary CPC classification H10F39/018. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Apr 05 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).