Data transmission circuit and data transmission method

Patent metadata

Field	Value
Publication number	US-12086025-B2
Application number	US-202217810015-A
Country	US
Kind code	B2
Filing date	Jun 30, 2022
Priority date	Feb 24, 2022
Publication date	Sep 10, 2024
Grant date	Sep 10, 2024

Abstract

A data transmission circuit and a data transmission method applied to the data transmission circuit are provided. The data transmission circuit includes: a data strobe module, connected to multiple memory blocks, connected to a low-bit data port through a first group of data buses, and connected to a high-bit data port through a second group of data buses, where each group of data buses include an odd data line and an even data line; and an error correction module, where each group of the data buses are provided with the error correction module, the error correction module is provided on the odd data line or the even data line, and the error correction module is configured to perform error correction on data written through the low-bit data port or the high-bit data port.

First claim

The invention claimed is:

1. A data transmission circuit, comprising:
a data strobe circuit, connected to multiple memory blocks, connected to a low-bit data port through a first group of data buses, and connected to a high-bit data port through a second group of data buses, wherein each of the first group of data buses and the second group of data buses comprise an odd data line and an even data line; and
two error correction circuits, wherein a first error correction circuit of the two error correction circuits is provided on the first group of data buses, a second error correction circuit of the two error correction circuits is provided on the second group of data buses, the two error correction circuits are provided on the odd data line or the even data line, the first error correction circuit is configured to perform error correction on data written through the low-bit data port, and the second error correction circuit is configured to perform error correction on data written through the high-bit data port.

2. The data transmission circuit according to claim 1 , wherein the first error correction circuit and the second error correction circuit are provided on a same type of data line.

3. The data transmission circuit according to claim 1 , wherein the data strobe circuit comprises a first data strobe and a second data strobe, the first data strobe is connected to a first group of memory blocks of the multiple memory blocks and is connected to the low-bit data port through the first group of data buses, the second data strobe is connected to a second group of memory blocks of the multiple memory blocks and is connected to the high-bit data port through the second group of data buses, a transmission bus is provided between the first data strobe and the second data strobe, the first group of data buses are connected to the second group of memory blocks through the first data strobe, the transmission bus, and the second data strobe, and the second group of data buses are connected to the first group of memory blocks through the second data strobe, the transmission bus, the first data strobe.

4. The data transmission circuit according to claim 3 , wherein the transmission bus comprises a first transmission bus and a second transmission bus.

5. The data transmission circuit according to claim 3 , wherein the first group of memory blocks comprise a first memory block and a second memory block, and the second group of memory blocks comprise a third memory block and a fourth memory block.

6. A data transmission method, applied to a data transmission circuit, the data transmission circuit comprising:
a data strobe circuit, connected to multiple memory blocks, connected to a low-bit data port through a first group of data buses, and connected to a high-bit data port through a second group of data buses, wherein each of the first group of data buses and the second group of data buses comprise an odd data line and an even data line; and
two error correction circuits, wherein a first error correction circuit of the two error correction circuits is provided on the first group of data buses, a second error correction circuit of the two error correction circuits is provided on the second group of data buses, the two error correction circuits are provided on the odd data line or the even data line, the first error correction circuit is configured to perform error correction on data written through the low-bit data port, and the second error correction circuit is configured to perform error correction on data written through the high-bit data port, and
the method comprising:
in response to a data write request, writing target data into a target memory block of the multiple memory blocks through a first-type data line or a second-type data line on which the first error correction circuit is provided in the first group of data buses and a first-type data line or a second-type data line on which the second error correction circuit is provided in the second group of data buses, wherein in the first group of data buses and the second group of data buses, one of the first-type data line or the second-type data line is provided with the first error correction circuit and the second error correction circuit, and the other is not provided with the first error correction circuit and the second error correction circuit.

7. The data transmission method according to claim 6 , wherein the first group of data buses are connected to a first data strobe, the first data strobe is connected to a first group of memory blocks of the multiple memory blocks, the second group of data buses are connected to a second data strobe, the second data strobe is connected to a second group of memory blocks of the multiple memory blocks, a transmission bus is provided between the first data strobe and the second data strobe, and the method further comprises:
during alternate writing of first data and second data, writing low-bit data of the first data and low-bit data of the second data through the first-type data line in the first group of data buses and the first data strobe, and writing high-bit data of the first data and high-bit data of the second data through the first-type data line in the second group of data buses and the second data strobe.

8. The data transmission method according to claim 7 , wherein during alternate writing of both the first data and the second data into the first group of memory blocks, the high-bit data of the first data and the high-bit data of the second data are written into the first group of memory blocks through the first-type data line in the second group of data buses, the second data strobe, two transmission buses in the transmission bus, and the first data strobe; and
during alternate writing of both the first data and the second data into the second group of memory blocks, the low-bit data of the first data and the low-bit data of the second data are written into the second group of memory blocks through the first-type data line in the first group of data buses, the first data strobe, the two transmission buses in the transmission bus, and the second data strobe.

9. The data transmission method according to claim 7 , wherein the transmission bus comprises a first transmission bus and a second transmission bus, and during respective writing of the first data and the second data into the first group of memory blocks and the second group of memory blocks,
the low-bit data of the first data is written into the first group of memory blocks through the first-type data line in the first group of data buses and the first data strobe;
the high-bit data of the first data is written into the first group of memory blocks through the first-type data line in the second group of data buses, the second data strobe, the first transmission bus, and the first data strobe;
the low-bit data of the second data is written into the second group of memory blocks through the first-type data line in the first group of data buses, the first data strobe, the second transmission bus, and the second data strobe; and
the high-bit data of the second data is written into the second group of memory blocks through the first-type data line in the second group of data buses and the second data strobe.

10. The data transmission method according to claim 6 , further comprising:
in response to a data read request, reading the target data from the target memory block through the first group of data buses and the second group of data buses.

11. The data transmission method according to claim 10 , wherein the first group of data buses are connected to a first data strobe, the first data strobe is connected to a first group of memory blocks of th

Assignees

• Changxin Memory Tech Inc

Inventors

• Ji Kangling

Classifications

• G06F13/4004 Primary

  Coupling between buses · CPC title

• G06F11/0745

  in an input/output transactions management context (input/output processing in general G06F13/00) · CPC title

• G06F11/1048

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G06F11/0793 Primary

  Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40) · CPC title