Error correction code decoders, semiconductor memory devices and memory systems

Patent metadata

Field	Value
Publication number	US-10846171-B2
Application number	US-201916371534-A
Country	US
Kind code	B2
Filing date	Apr 1, 2019
Priority date	Nov 6, 2018
Publication date	Nov 24, 2020
Grant date	Nov 24, 2020

Abstract

An error correction code (ECC) decoder of a semiconductor memory device is provided. The ECC decoder includes an ECC checker, a syndrome generator, and an error detection/correction circuit. The ECC checker generates characteristic information representing first error information associated with message bits in an input codeword that is read from a target page in a memory cell array. The syndrome generator outputs a syndrome vector representing second error information associated with the input codeword by performing an operation on the message bits and parity bits in the input codeword based on a parity check matrix. The an error detection/correction circuit generates a transmission codeword by selectively correcting an error bit in the input codeword based on the characteristic information and the syndrome vector, generates a flag signal indicating whether the transmission codeword includes an error bit, and outputs a transmission message based on the transmission codeword.

First claim

What is claimed is:

1. An error correction code (ECC) decoder of a semiconductor memory device, the ECC decoder comprising:
an ECC checker configured to generate characteristic information representing first error information associated with message bits in an input codeword that is read from a target page in a memory cell array;
a syndrome generator configured to output a syndrome vector representing second error information associated with the input codeword by performing an operation on the message bits and parity bits in the input codeword based on a parity check matrix; and
an error detection/correction circuit configured to generate a transmission codeword by selectively correcting an error bit in the input codeword based on the characteristic information and the syndrome vector, generate a flag signal indicating whether the transmission codeword includes an error bit, and output a transmission message based on the transmission codeword.

2. The ECC decoder of claim 1 , wherein the parity check matrix includes:
a first part corresponding to the message bits; and
a second part corresponding to the parity bits,
wherein the first part includes a plurality of column vectors, each including an even number of high-level elements,
wherein the second part includes a plurality of parity column vectors, each including an odd number of high-level elements,
wherein the parity check matrix corresponds to a first type of parity check matrix that includes a plurality of different row vectors and a plurality of different column vectors, and
wherein the ECC checker is configured to perform a first modulo-two operation on a first sum of the message bits to output a first result of the first modulo-two operation, associated with the first error information, as the characteristic information.

3. The ECC decoder of claim 2 , wherein the error detection/correction circuit is configured to:
generate a summed signal by calculating a second sum of elements of the syndrome vector;
perform selectively a second modulo-two operation on a third sum of the summed signal and the characteristic information, based on whether the third sum corresponds to zero;
correct selectively the input codeword based on the summed signal and a second result of the second modulo-two operation; and
generate the flag signal.

4. The ECC decoder of claim 2 , wherein the error detection/correction circuit includes:
a summer configured to generate a summed signal by calculating a second sum of elements of the syndrome vector;
an error detector configured to generate a detection signal indicating whether the input codeword includes an error bit based on whether a third sum of the summed signal and the characteristic information corresponds to zero;
a modulo calculator configured to perform a second modulo-two operation on the third sum in response to the third sum being non-zero to generate a modulo signal indicating whether a second result of the second modulo-two operation is zero;
a data corrector configured to selectively correct the input codeword to generate the transmission codeword, based on the summed signal and the modulo signal;
a message extractor configured to extract a transmission message from the transmission codeword and to output the transmission message; and
a flag generator configured to generate the flag signal indicating whether the transmission codeword includes an error bit based on the detection signal and the modulo signal.

5. The ECC decoder of claim 4 , wherein the flag generator is configured to output the flag signal with a first logic level in response to the detection signal indicating that the transmission codeword includes no error bit.

6. The ECC decoder of claim 4 , wherein:
the modulo calculator is configured to perform the second modulo-two operation in response to the detection signal indicating that the transmission codeword includes the error bit;
the data corrector is configured to correct the error bit in the input codeword to generate the transmission codeword in response to the modulo signal indicating that the second result of the second modulo-two operation is non-zero; and
the flag generator is configured to output the flag signal with a first logic level in response to the detection signal and the modulo signal to represent that the transmission message includes no error bit.

7. The ECC decoder of claim 4 , wherein:
the modulo calculator is configured to perform the second modulo-two operation in response to the detection signal indicating that the transmission codeword includes the error bit;
the data corrector is configured to output the transmission codeword without correcting the error bit in the transmission codeword in response to the modulo signal indicating that the second result of the second modulo-two operation is zero; and
the flag generator is configured to output the flag signal with a second logic level in response to the detection signal and the modulo signal to represent that the transmission message includes an error bit.

8. The ECC decoder of claim 1 , wherein the parity check matrix includes:
a first part corresponding to the message bits; and
a second part corresponding to the parity bits,
wherein a first row vector of a plurality of row vectors of the parity check matrix includes a first sub part corresponding to the first part and a second sub part corresponding to the second part, all elements in the first sub part have a low level, and all elements in the second sub part have a high level,
the parity check matrix corresponds to a second type of parity check matrix that includes the plurality of different row vectors and a plurality of different column vectors, and
wherein the ECC checker is configured to perform a first modulo-two operation on a first sum of the message bits to output a first result of the first modular-two operation, associated with the first error information, as the characteristic information.

9. The ECC decoder of claim 8 , wherein the error detection/correction circuit is configured to:
generate a summed signal by calculating a second sum of elements of the syndrome vector;
perform selectively a second modulo-two operation on a third sum of the characteristic information and a selected element in the syndrome vector based on whether a fourth sum of the summed signal and the characteristic information corresponds to zero, the selected element corresponding to the first row vector;
correct selectively the input codeword based on the summed signal and a second result of the second modulo-two operation; and
generate the flag signal.

10. The ECC decoder of claim 8 , wherein the error detection/correction circuit includes:
a summer configured to generate a summed signal by calculating a second sum of elements of the syndrome vector;
an error detector configured to generate a detection signal indicating whether the input codeword includes an error bit, based on whether a third sum of the summed signal and the characteristic information corresponds to zero;
a modulo calculator configured to perform a second modulo-two operation on a fourth sum of the characteristic information and the selected element in response to the third sum being non-zero to generate a modulo signal indicating whether a second result of the second modulo-two operation is zero;
a data corrector configured to selectively correct the input codeword to generate the transmission codeword, based on the detection signal and the modulo signal;
a message extractor configured to extract a transmission message from the transmission codeword and to output the transmission message; and
a flag generator configured to generate the flag signal indicating whether the tran

Assignees

• Samsung Electronics Co Ltd

Inventors

• Cho Sung-Hye
• Lee Ki-Jun
• Lee Myung-Kyu
• Kong Jun Jin

Classifications

• H03M13/1575 Primary

  Direct decoding, e.g. by a direct determination of the error locator polynomial from syndromes and subsequent analysis or by matrix operations involving syndromes, e.g. for codes with a small minimum Hamming distance · CPC title

• H03M13/1148

  Structural properties of the code parity-check or generator matrix · CPC title

• G11B20/1037

  based on hard decisions, e.g. by evaluating bit error rates before or after ECC decoding · CPC title

• G11C29/52 Primary

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G11C29/42 Primary

  using error correcting codes [ECC] or parity check · CPC title