Semiconductor memory devices and methods of operating semiconductor memory devices

Patent metadata

Field	Value
Publication number	US-11314592-B2
Application number	US-202016909730-A
Country	US
Kind code	B2
Filing date	Jun 23, 2020
Priority date	Dec 23, 2019
Publication date	Apr 26, 2022
Grant date	Apr 26, 2022

Abstract

A semiconductor memory device includes a memory cell array, an error correction circuit and a control logic circuit. The error correction circuit includes an error correction code (ECC) decoder to perform an ECC decoding on a codeword including a main data and a parity data, read from a target page of the memory cell array to correct errors in the read codeword. The control logic circuit controls the error correction circuit based on a command and address from an external memory controller. The ECC decoder has t-bit error correction capability, generates a syndrome based on the codeword using a parity check matrix, performs t iterations during (t−2) cycles to generate an error locator polynomial based on the syndrome, searches error positions in the codeword based on the error locator polynomial and corrects the errors in the codeword based on the searched error positions.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
a memory cell array comprising a plurality of memory cells coupled to word-lines and bit-lines, the memory cell array further comprising a plurality of sense amplifiers configured to sense data stored in the plurality of memory cells;
an error correction circuit comprising an error correction code (ECC) decoder configured to perform an ECC decoding on a codeword read from a target page of the memory cell array to correct errors in the codeword that was read, the codeword comprising a main data and a parity data; and
a control logic circuit configured to control the error correction circuit based on a command and address from an external memory controller,
wherein the ECC decoder is configured to perform operations comprising:
performing t-bit error correction, wherein t is an even integer greater than three;
generating a syndrome based on the codeword using a parity check matrix;
performing t iterations during (t−2) cycles to generate an error locator polynomial based on the syndrome;
searching error positions in the codeword based on the error locator polynomial; and
correcting the errors in the codeword based on the error positions that were searched.

2. The semiconductor memory device of claim 1 , wherein the ECC decoder comprises:
a syndrome generator configured to generate the syndrome by performing a matrix-multiplication operation on the codeword and the parity check matrix;
a Berlekamp-Massey (BM) generator configured to generate coefficients of the error locator polynomial during the (t−2) cycles based on the syndrome;
a chien search block configured to search the error positions based on the coefficients of the error locator polynomial to output an error position signal; and
a data corrector configured to receive the codeword and configured to correct the errors in the codeword based on the error position signal.

3. The semiconductor memory device of claim 2 , wherein the BM generator comprises:
a shared processing element;
(3t/2+2) processing elements connected to the shared processing element; and
a controller configured to control the shared processing element and the (3t/2+2) processing elements,
wherein the shared processing element is configured to perform a 0-th iteration and a first iteration during a 0-th cycle based on the syndrome to generate second iteration intermediate coefficients associated with a second iteration, and is configured to provide the second iteration intermediate coefficients to the (3t/2+2) processing elements,
wherein the (3t/2+2) processing elements are configured to perform the second iteration through (t−2)-th iterations based on the second iteration intermediate coefficients to provide the shared processing element with (t−1)-th iteration coefficients associated with a (t−1)-th iteration, and
wherein the shared processing element is configured to perform the (t−1)-th iteration based on the (t−1)-th iteration coefficients to generate the coefficients of the error locator polynomial.

4. The semiconductor memory device of claim 3 , wherein the shared processing element is configured to perform the (t−1)-th iteration by using circuits configured to generate the second iteration intermediate coefficients.

5. The semiconductor memory device of claim 3 , wherein the shared processing element comprises:
a first intermediate coefficient generator configured to generate auxiliary coefficients of an auxiliary polynomial among the second iteration intermediate coefficients, based on the syndrome and a first control signal;
a second intermediate coefficient generator configured to generate difference coefficients of a difference polynomial and coefficients of the error locator polynomial among the second iteration intermediate coefficients, based on the (t−1)-th iteration coefficients, the first control signal, and a second control signal; and
a control signal generator configured to generate the second control signal based on the syndrome.

6. The semiconductor memory device of claim 5 , wherein the first intermediate coefficient generator comprises:
a first sub generator configured to generate an i-th auxiliary coefficient among the auxiliary coefficients based on the syndrome, the first control signal, and the second control signal, when i is in an interval 0≤i≤(t/2)−1;
a second sub generator configured to generate the i-th auxiliary coefficient based on the first control signal and the second control signal when i=t−1 or i=t−2; and
a third sub generator configured to generate the i-th auxiliary coefficient based on a first sub syndrome of the syndrome, the first control signal and the second control signal, when i=(3t/2) or i=(3t/2)+1.

7. The semiconductor memory device of claim 6 ,
wherein the first sub generator comprises a Galois field multiplier, an exclusive OR gate, and a first multiplexer;
wherein the second sub generator comprises first registers and a second multiplexer; and
wherein the third sub generator comprises second registers, a third multiplexer, and a fourth multiplexer.

8. The semiconductor memory device of claim 5 , wherein the second intermediate coefficient generator comprises:
a first sub generator configured to generate the difference coefficients and the coefficients of the error locator polynomial based on the syndrome, the difference coefficients, an auxiliary difference value, and an iteration control signal designating the (t−2)-th iteration;
a second sub generator configured to generate a (t−2)-th difference coefficient and a ((t−2)+1)-th difference coefficient of the difference coefficients based on the syndrome and the first control signal; and
a third sub generator configured to generate a (3t/2)-th difference coefficient and a ((3t/2)+1)-th difference coefficient of the difference coefficients based on the syndrome and the first control signal.

9. The semiconductor memory device of claim 8 ,
wherein the first sub generator comprises a plurality of first multiplexers, a plurality of first Galois field multipliers, and a plurality of first exclusive OR gates;
wherein the second sub generator comprises first registers, a second Galois field multiplier, a second exclusive OR gate, and second multiplexers; and
wherein the third sub generator comprises a second register and a third multiplexer.

10. The semiconductor memory device of claim 9 , wherein the first sub generator is configured to generate the second iteration intermediate coefficients and to perform the (t−1)-th iteration by using a one or more of the plurality of first multiplexers, the first Galois field multipliers, and the plurality of first exclusive OR gates.

11. The semiconductor memory device of claim 5 , wherein the control signal generator comprises:
a Galois field multiplier configured to perform a Galois field multiplication on a first sub syndrome and a second sub syndrome of the syndrome;
an exclusive OR gate configured to perform an exclusive OR on an output of the Galois field multiplier and a third sub syndrome of the syndrome; and
an OR gate configured to perform an OR operation on an output of the exclusive OR gate to provide the second control signal.

12. The semiconductor memory device of claim 3 , wherein the (3t/2+2) processing elements are sequentially connected and are configured to perform the second iteration in a second cycle based on the second iteration intermediate coefficients, and to perform a corresponding iteration in each of third through (t−2)-th cycles based on outputs of a previous processing element among the (3t/2+2) processing elements.

13. The semiconductor memory device of cl

Assignees

• Samsung Electronics Co Ltd

Inventors

• Song Yeonggeol
• Kim Sungrae
• Lee Kijun

Classifications

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/00 Primary

  Package configurations · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/247

  Dispositions of multiple bumps · CPC title

• H10W72/07254

  changes in dispositions · CPC title