Three-dimensional memory devices having first semiconductor structure bonded with second semiconductor structure each including peripheral circuit and methods for forming the same

Patent metadata

Field	Value
Publication number	US-12082408-B2
Application number	US-202117481803-A
Country	US
Kind code	B2
Filing date	Sep 22, 2021
Priority date	Jun 30, 2021
Publication date	Sep 3, 2024
Grant date	Sep 3, 2024

Abstract

In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first and second semiconductor structures. The first semiconductor structure includes an array of NAND memory strings, a first peripheral circuit of the array of NAND memory strings including a first transistor, a polysilicon layer between the array of NAND memory strings and the first peripheral circuit, and a first semiconductor layer in contact with the first transistor. The polysilicon layer is in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a second peripheral circuit of the array of NAND memory strings including a second transistor, and a second semiconductor layer in contact with the second transistor. The second peripheral circuit is between the bonding interface and the second semiconductor layer. The first semiconductor layer is between the polysilicon layer and the second semiconductor layer.

First claim

What is claimed is:

1. A three-dimensional (3D) memory device, comprising:
a first semiconductor structure, comprising:
an array of NAND memory strings;
a first peripheral circuit of the array of NAND memory strings, the first peripheral circuit comprising a first transistor;
a polysilicon layer between the array of NAND memory strings and the first peripheral circuit, the polysilicon layer being in contact with sources of the array of NAND memory strings; and
a first semiconductor layer in contact with the first transistor;

a second semiconductor structure, comprising:
a second peripheral circuit of the array of NAND memory strings, the second peripheral circuit comprising a second transistor; and
a second semiconductor layer in contact with the second transistor; and

a bonding interface between the first semiconductor structure and the second semiconductor structure,
wherein the second peripheral circuit is between the bonding interface and the second semiconductor layer; and
the first semiconductor layer is between the polysilicon layer and the second semiconductor layer.

2. The 3D memory device of claim 1 , wherein the first peripheral circuit is between the first semiconductor layer and the polysilicon layer.

3. The 3D memory device of claim 1 , wherein each of the first and second semiconductor layers comprises single crystalline silicon.

4. The 3D memory device of claim 1 , wherein a thickness of the second semiconductor layer is greater than a thickness of the first semiconductor layer.

5. The 3D memory device of claim 1 , wherein
the first transistor comprises a first gate dielectric;
the second transistor comprises a second gate dielectric; and
a thickness of the second gate dielectric is greater than a thickness of the first gate dielectric.

6. The 3D memory device of claim 5 , wherein a difference between the thickness of the first gate dielectric and the thickness of the second gate dielectric is at least 5-fold.

7. The 3D memory device of claim 5 , wherein
the first semiconductor structure further comprises a third peripheral circuit of the array of NAND memory strings, the third peripheral circuit comprising a third transistor that comprises a third gate dielectric; and
the second semiconductor structure further comprises a fourth peripheral circuit of the array of NAND memory strings, the fourth peripheral circuit comprising a fourth transistor that comprises a fourth gate dielectric.

8. The 3D memory device of claim 7 , wherein the third and fourth gate dielectrics have a same thickness.

9. The 3D memory device of claim 8 , wherein the thicknesses of the third and fourth gate dielectrics is between the thicknesses of the first and second gate dielectrics.

10. The 3D memory device of claim 7 , wherein the third and fourth peripheral circuits comprise at least one of a page buffer circuit or a logic circuit.

11. The 3D memory device of claim 1 , wherein
the first semiconductor structure further comprises a first interconnect layer between the polysilicon layer and the first peripheral circuit, the first interconnect layer comprising a first interconnect coupled to the first transistor; and
the second semiconductor structure further comprises a second interconnect layer between the bonding interface and the second peripheral circuit, the second interconnect layer comprising a second interconnect coupled to the second transistor.

12. The 3D memory device of claim 11 , wherein the first interconnect comprises tungsten.

13. The 3D memory device of claim 11 , wherein the first semiconductor structure further comprises:
a third interconnect layer, the array of NAND memory strings being arranged between the third interconnect layer and the polysilicon layer, and the third interconnect layer comprising a third interconnect coupled to the array of NAND memory strings;
a first contact extending through the polysilicon layer and coupling the third interconnect to the first interconnect; and
a second contact extending through the first semiconductor layer and coupling the first interconnect to the second interconnect.

14. The 3D memory device of claim 1 , wherein
the first semiconductor structure further comprises a first pad-out interconnect layer above the array of NAND memory strings; or
the second semiconductor structure further comprises a second pad-out interconnect layer in contact with the second semiconductor layer.

15. The 3D memory device of claim 1 , wherein the second peripheral circuit comprises a driving circuit, and the first peripheral circuit comprises an input/output (I/O) circuit.

16. The 3D memory device of claim 1 , further comprising:
a first voltage source coupled to the first peripheral circuit and configured to provide a first voltage to the first peripheral circuit; and
a second voltage source coupled to the second peripheral circuit and configured to provide a second voltage to the second peripheral circuit,
wherein the second voltage is greater than the first voltage.

17. The 3D memory device of claim 1 , wherein
the first semiconductor structure further comprises a first bonding layer, the first semiconductor layer being arranged between the first bonding layer and the first peripheral circuit, and the first bonding layer comprising a first bonding contact;
the second semiconductor structure further comprises a second bonding layer, the second peripheral circuit being arranged between the second bonding layer and the second semiconductor layer, the second bonding layer comprising a second bonding contact; and
the first bonding contact is in contact with the second bonding contact at the bonding interface.

18. The 3D memory device of claim 1 , wherein the first transistor is formed on the first semiconductor layer, and the second transistor is formed on the second semiconductor layer.

19. The 3D memory device of claim 1 , wherein the first semiconductor structure further comprises a third peripheral circuit of the array of NAND memory strings, a first voltage provided to the first peripheral circuit being higher than a third voltage provided to the third peripheral circuit.

20. The 3D memory device of claim 1 , wherein the second semiconductor structure further comprises a fourth peripheral circuit of the array of NAND memory strings, a second voltage provided to the second peripheral circuit being higher than a fourth voltage provided to the fourth peripheral circuit.

Assignees

• Yangtze Memory Tech Co Ltd
• Yangtze Memory Tech Co ˜Ltd

Inventors

• Yang Yuancheng
• Zhou Wenxi
• Xia Zhiliang
• Liu Wei

Classifications

• H10W80/00

  Direct bonding of chips, wafers or substrates · CPC title

• H10W20/2134

  TSVs extending from the semiconductor wafer into back-end-of-line layers · CPC title

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W20/2125

  Top-view shapes · CPC title

• H10W20/0242

  comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title