Fabrication of thin film fin transistor structure

Patent metadata

Field	Value
Publication number	US-12080781-B2
Application number	US-202017129867-A
Country	US
Kind code	B2
Filing date	Dec 21, 2020
Priority date	Dec 21, 2020
Publication date	Sep 3, 2024
Grant date	Sep 3, 2024

Abstract

Thin film transistors fabricated using a spacer as a fin are described. In an example, a method of forming a fin transistor structure includes patterning a plurality of backbone pillars on a semiconductor substrate. The method may then include conformally depositing a spacer layer over the plurality of backbone pillars and the semiconductor substrate. A spacer etch of the spacer layer is then performed to leave a sidewall of the spacer layer on a backbone pillar to form a fin of the fin transistor structure. Other embodiments may be described and claimed.

First claim

What is claimed is:

1. A method of forming a fin transistor structure, comprising:
patterning a plurality of backbone pillars on a semiconductor substrate;
conformally depositing a spacer layer over the plurality of backbone pillars and the semiconductor substrate; and
performing a spacer etch of the spacer layer to leave a first sidewall and a second sidewall of the spacer layer on a backbone pillar to form a first fin and a second fin, respectively, of the fin transistor structure, wherein the first fin has a first side higher than a second side, and the second fin has a first side higher than a second side, and wherein the first side of the first fin faces toward the first side of the second fin.

2. The method of claim 1 , wherein conformally depositing the spacer layer includes conformally depositing a channel material over the plurality of backbone pillars.

3. The method of claim 2 , wherein the channel material is selected from one or more of a semiconductor material comprising oxides, sulphides, selenides, nitrides or carbides including one more of indium, gallium, zinc, tin, titanium, ruthenium, and tungsten, molybdenum, copper, niobium, nickel, lead, tantalum, and hafnium.

4. The method of claim 1 , wherein the plurality of backbone pillars include one or more of silicon (Si), silicon nitride (SiN), silicon oxide (SiO 2 ), carbon (C), silicon carbide (SiC), silicon oxynitride (SiON), and carbon-doped oxide (CDO).

5. The method of claim 1 , further comprising after performing the spacer etch of the spacer layer, etching the plurality of backbone pillars to remove the backbone pillars.

6. The method of claim 1 , further comprising after performing the spacer etch of the spacer layer, allowing the plurality of backbone pillars to remain as a support for the first fin and the second fin.

7. An integrated circuit structure, comprising:
a substrate; and
a fin transistor structure above the substrate, the fin transistor structure comprising a first fin and a second fin of a channel material, wherein the first fin has a first side higher than a second side, and the second fin has a first side higher than a second side, and wherein the first side of the first fin faces toward the first side of the second fin.

8. The integrated circuit structure of claim 7 , wherein the channel material is selected from one or more of a semiconductor material comprising oxides, sulphides, selenides, nitrides or carbides including one more of indium, gallium, zinc, tin, titanium, ruthenium, and tungsten, molybdenum, copper, niobium, nickel, lead, tantalum, and hafnium.

9. The integrated circuit structure of claim 7 , wherein a backbone pillar is between the first fin and the second fin.

10. The integrated circuit structure of claim 9 , wherein the integrated circuit structure comprises a tri-gate transistor and the backbone pillar remains to provide support for the tri-gate transistor.

11. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a substrate; and
a fin transistor structure above the substrate, the fin transistor structure comprising a first fin and a second fin of a channel material, wherein the first fin has a first side higher than a second side, and the second fin has a first side higher than a second side, and wherein the first side of the first fin faces toward the first side of the second fin.

12. The computing device of claim 11 , wherein the further comprising a backbone pillar between the first fin and the second fin.

13. The computing device of claim 11 , further comprising a communication chip coupled to the board.

14. The computing device of claim 11 , further comprising: a memory coupled to the board.

15. The computing device of claim 11 , wherein the component is a packaged integrated circuit die.

Assignees

• Intel Corp

Inventors

• Sato Noriyuki
• Atanasov Sarah
• Sharma Abhishek A
• Sell Bernhard
• Ku Chieh-Jen
• Tan Elliot N
• Yoo Hui Jae
• Lajoie Travis W
• Le Van H
• Wang Pei-Hua
• Peck Jason
• Brown-Heft Tobias

Classifications

• H10D30/62 Primary

  Fin field-effect transistors [FinFET] · CPC title

• H10D30/024 Primary

  of fin field-effect transistors [FinFET] · CPC title

• H10D84/853

  comprising FinFETs · CPC title

• H10D84/0158

  the components including FinFETs · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title