Semiconductor device structure and methods of forming the same

Patent metadata

Field	Value
Publication number	US-12080751-B2
Application number	US-202217742452-A
Country	US
Kind code	B2
Filing date	May 12, 2022
Priority date	May 12, 2022
Publication date	Sep 3, 2024
Grant date	Sep 3, 2024

Abstract

Semiconductor device structure and methods of forming the same are described. The structure includes a first dielectric layer including a first portion disposed over a source/drain region in an active region of a substrate and a modulation portion over an interlayer dielectric (ILD) in a resistor region of the substrate, the first portion of the first dielectric layer has a first composition, and the modulation portion of the first dielectric layer has a second composition different from the first composition. The structure further includes a resistor layer disposed on the modulation portion of the first dielectric layer in the resistor region and a second dielectric layer disposed over the first dielectric layer in the active region and over the resistor layer in the resistor region.

First claim

The invention claimed is:

1. A method, comprising:
forming a first dielectric layer over a source/drain region in an active region and over an interlayer dielectric (ILD) in a resistor region;
forming a first mask layer on the first dielectric layer, wherein a portion of the first dielectric layer in the resistor region is exposed;
performing an implantation process to implant a dopant into the exposed portion of the first dielectric layer to form a modulation portion in the resistor region;
forming a resistor layer on the first dielectric layer in the active region and on the modulation portion in the resistor region;
forming a second mask layer on the resistor layer;
removing portions of the resistor layer and second mask layer disposed in the active region to expose a portion of the first dielectric layer; and
forming a second dielectric layer on the exposed portion of the first dielectric layer in the active region and on the second mask layer in the resistor region.

2. The method of claim 1 , further comprising forming conductive features in the second mask layer, the resistor layer, and the modulation portion of the first dielectric layer.

3. The method of claim 2 , wherein the removing portions of the resistor layer and second mask layer disposed in the active region also removes a portion of the first dielectric layer.

4. The method of claim 2 , wherein the removing portions of the resistor layer and second mask layer disposed in the active region also removes a portion of the modulation portion.

5. The method of claim 1 , further comprising forming a patterned mask layer on the second mask layer, wherein a width of the patterned mask layer is substantially the same or less than a width of the modulation portion.

6. A method, comprising:
depositing a first dielectric layer over an interlayer dielectric (ILD);
depositing a mask layer on the first dielectric layer;
forming an opening in the mask layer to expose a first portion of the first dielectric layer;
introducing a dopant into the exposed first portion of the first dielectric layer to form a modulation portion;
removing the mask layer to expose a second portion of the first dielectric layer;
depositing a resistor layer on the second portion of the first dielectric layer and on the modulation portion;
removing portions of the resistor layer to expose the second portion of the first dielectric layer; and
depositing a second dielectric layer on the exposed second portion of the first dielectric layer and over the resistor layer.

7. The method of claim 6 , wherein the first dielectric layer is disposed over a gate structure and a source/drain region.

8. The method of claim 7 , wherein the second portion of the first dielectric layer is disposed over the gate structure and the source/drain region.

9. The method of claim 8 , wherein the second dielectric layer is disposed over the gate structure and the source/drain region.

10. The method of claim 6 , wherein the introducing the dopant is performed by an implantation process.

11. The method of claim 6 , wherein the introducing the dopant is performed by depositing a dopant-rich layer on the exposed first portion of the first dielectric layer and diffusing the dopant from the dopant-rich layer into the first portion of the first dielectric layer.

12. The method of claim 6 , wherein the dopant is introduced through a portion of a thickness of the first portion of the first dielectric layer.

13. The method of claim 6 , wherein the dopant is introduced through an entire thickness of the first portion of the first dielectric layer.

14. A method, comprising:
depositing a first dielectric layer over an interlayer dielectric (ILD);
introducing a dopant into a first portion of the first dielectric layer to form a modulation portion;
depositing a resistor layer on a second portion of the first dielectric layer and on the modulation portion;
depositing a first mask layer on the resistor layer;
removing portions of the first mask layer and portions of the resistor layer to expose the second portion of the first dielectric layer; and
depositing a second dielectric layer on the exposed second portion of the first dielectric layer and on the first mask layer.

15. The method of claim 14 , wherein the removing the portions of the first mask layer and the portions of the resistor layer are performed by one or more etch processes.

16. The method of claim 15 , wherein the one or more etch processes remove portions of the modulation portion.

17. The method of claim 14 , wherein the second dielectric layer is in contact with sidewalls of the resistor layer and sidewalls of the first mask layer.

18. The method of claim 14 , further comprising depositing a second mask layer on the first dielectric layer and forming an opening in the second mask layer to expose the first portion of the first dielectric layer.

19. The method of claim 18 , further comprising removing the second mask layer after the introducing of the dopant into the first portion of the first dielectric layer.

20. The method of claim 14 , further comprising forming a conductive feature through the first mask layer, the resistor layer, and into the modulation portion.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lu Hsueh-Han
• Chen Kun-Ei
• Chiang Chen-Chieh
• Wang Ling-Sung
• Nian Jun-Nan

Classifications

• H10P32/20

  Diffusion for doping of insulating layers · CPC title

• H10W20/095

  by irradiating with electromagnetic or particle radiation (plasma treatment H10W20/096) · CPC title

• H10W20/093

  by modifying materials of the dielectric parts · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/498

  Resistive arrangements or effects of, or between, wiring layers · CPC title