Methods and systems for manufacturing semiconductor devices

Patent metadata

Field	Value
Publication number	US-12080678-B2
Application number	US-202217881572-A
Country	US
Kind code	B2
Filing date	Aug 4, 2022
Priority date	Dec 28, 2018
Publication date	Sep 3, 2024
Grant date	Sep 3, 2024

Abstract

A thermocompression bonding (TCB) apparatus can include a wall having a height measured in a first direction and configured to be positioned between a first pressing surface and a second pressing surface of a semiconductor bonding apparatus. The apparatus can include a cavity at least partially surrounded by the wall, the cavity sized to receive a semiconductor substrate and a stack of semiconductor dies positioned between the semiconductor substrate and the first pressing surface, the stack of semiconductor dies and semiconductor substrate having a combined unpressed stack height as measured in the first direction. In some embodiments, the unpressed stack height is greater than the height of the wall, and the wall is configured to be contacted by the first pressing surface to limit movement of the first pressing surface toward the second pressing surface during a semiconductor bonding process.

First claim

We claim:

1. A semiconductor manufacturing system comprising:
a first press-stage having a first pressing surface;
a second press-stage having a second pressing surface facing the first pressing surface;
a stopper positioned between the first press-stage and the second press-stage, the stopper comprising at least one internal cavity and a continuous wall surrounding the at least one internal cavity, the continuous wall and at least one internal cavity configured to receive a stack of semiconductor dies;
wherein the stopper is configured to limit movement of the first and second pressing surfaces toward each other to limit compression of the first stack of the semiconductor to a desired thickness.

2. The semiconductor manufacturing system of claim 1 , wherein the stopper is formed integrally with the second stage.

3. The semiconductor manufacturing system of claim 1 , wherein the stopper is constructed from one or more of silicon, metal, polymer, and glass.

4. The semiconductor manufacturing system of claim 1 , wherein the stopper comprises a second cavity configured to receive a second stack of semiconductor dies.

5. The semiconductor manufacturing system of claim 1 , wherein the stopper is positioned between the semiconductor substrate and the first press-stage.

6. The semiconductor manufacturing system of claim 1 , wherein the stopper has an annular shape.

7. A semiconductor bonding apparatus comprising:
a first stage of a having a first pressing surface;
a second stage having a second pressing surface facing the first pressing surface;
a stopper wall at least partially surrounding a cavity configured to a stack of semiconductor dies, and wherein the stopper wall has a stopper height measured from the second pressing surface in a direction normal to the first pressing surface and configured to stop a relative movement of the first and second pressing surfaces toward each other at a distance less than or equal to the stopper height.

8. The semiconductor bonding apparatus of claim 7 , wherein the stopper wall is constructed from one or more of silicon, metal, polymer, and glass.

9. The semiconductor bonding apparatus of claim 7 , wherein the stopper wall is annular.

10. The semiconductor bonding apparatus of claim 7 , wherein the stopper wall is permanently connected to the second stage of the semiconductor bonding apparatus.

11. The semiconductor bonding apparatus of claim 7 , wherein the stopper comprises a second cavity configured to receive a second stack of semiconductor dies.

Assignees

• Micron Technology Inc

Inventors

• Zhou Wei
• Street Bret K
• Mcclain Benjamin L
• Tuttle Mark E

Classifications

• H10W72/07232

  Compression bonding, e.g. thermocompression bonding · CPC title

• H10W72/07141

  Means for applying energy, e.g. ovens or lasers · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W72/07338

  hardening the adhesive by curing, e.g. thermosetting · CPC title