Integrated circuit structures having differentiated interconnect lines in a same dielectric layer

Patent metadata

Field	Value
Publication number	US-12080643-B2
Application number	US-201916583691-A
Country	US
Kind code	B2
Filing date	Sep 26, 2019
Priority date	Sep 26, 2019
Publication date	Sep 3, 2024
Grant date	Sep 3, 2024

Abstract

Integrated circuit structures having differentiated interconnect lines in a same dielectric layer, and methods of fabricating integrated circuit structures having differentiated interconnect lines in a same dielectric layer, are described. In an example, an integrated circuit structure includes an inter-layer dielectric (ILD) layer above a substrate. A plurality of conductive interconnect lines is in the ILD layer. The plurality of conductive interconnect lines includes a first interconnect line having a first height, and a second interconnect line immediately laterally adjacent to but spaced apart from the first interconnect line, the second interconnect line having a second height less than the first height.

First claim

What is claimed is:

1. An integrated circuit structure, comprising:
an inter-layer dielectric (ILD) layer above a substrate; and
a plurality of conductive interconnect lines in the ILD layer, the plurality of conductive interconnect lines comprising:
a first conductive interconnect line; and
a second conductive interconnect line immediately adjacent to the first conductive interconnect line, the second conductive interconnect line having a bottommost surface above a bottommost surface of the first conductive interconnect line, and the second conductive interconnect line having an uppermost surface below an uppermost surface of the first conductive interconnect line, wherein the ILD layer is on the uppermost surface of the second conductive interconnect line,
wherein the second conductive interconnect line has a width less than a width of the first conductive interconnect line.

2. The integrated circuit structure of claim 1 , wherein the uppermost surface of the first conductive interconnect line is co-planar with a top surface of the ILD layer.

3. The integrated circuit structure of claim 1 , further comprising:
an etch stop layer on the ILD layer.

4. The integrated circuit structure of claim 1 , wherein the first conductive interconnect line is defined by a first lithographic process, and the second conductive interconnect line is defined by a second lithographic process.

5. The integrated circuit structure of claim 1 , wherein the first conductive interconnect line has a same composition as the second conductive interconnect line.

6. The integrated circuit structure of claim 1 , wherein the first conductive interconnect line has a different composition than the second conductive interconnect line.

7. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
an inter-layer dielectric (ILD) layer above a substrate; and
a plurality of conductive interconnect lines in the ILD layer, the plurality of conductive interconnect lines comprising:
a first conductive interconnect line; and
a second conductive interconnect line immediately adjacent to the first conductive interconnect line, the second conductive interconnect line having a bottommost surface above a bottommost surface of the first conductive interconnect line, and the second conductive interconnect line having an uppermost surface below an uppermost surface of the first conductive interconnect line, wherein the ILD layer is on the uppermost surface of the second interconnect line,

wherein the second conductive interconnect line has a width less than a width of the first conductive interconnect line.

8. The computing device of claim 7 , further comprising:
a memory coupled to the board.

9. The computing device of claim 7 , further comprising:
a camera coupled to the board.

10. The computing device of claim 7 , further comprising:
a battery coupled to the board.

11. The computing device of claim 7 , wherein the component is a packaged integrated circuit die.

12. The computing device of claim 7 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.

13. The computing device of claim 7 , wherein the computing device is selected from the group consisting of a mobile phone, a laptop, a desk top computer, a server, and a set-top box.

Assignees

• Intel Corp

Inventors

• Lajoie Travis W
• Sharma Abhishek A
• Alzate Vinasco Juan G
• Ku Chieh-Jen
• Ogadhoh Shem O
• Gardiner Allen B
• Lin Blake C
• Wang Yih
• Wang Pei-Hua
• Kavalieros Jack T
• Sell Bernhard
• Ghani Tahir

Classifications

• H10W20/496

  Capacitor integral with wiring layers · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/074

  of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/435 Primary

  Cross-sectional shapes or dispositions of interconnections · CPC title