Three dimensional (3D) integrated circuits (ICs) (3DICs) and related systems

Patent metadata

Field	Value
Publication number	US-9343369-B2
Application number	US-201414280731-A
Country	US
Kind code	B2
Filing date	May 19, 2014
Priority date	May 19, 2014
Publication date	May 17, 2016
Grant date	May 17, 2016

Abstract

Methods for constructing three dimensional integrated circuits and related systems are disclosed. In one aspect, a first tier is constructed by creating active elements such as transistors on a holding substrate. An interconnection metal layer is created above the active elements. Metal bonding pads are created within the interconnection metal layer. A second tier is also created, either concurrently or sequentially. The second tier is created in much the same manner as the first tier and is then placed on the first tier, such that the respective metal bonding pads align and are bonded one tier to the other. The holding substrate of the second tier is then released. A back side of the second tier is then thinned, such that the back surfaces of the active elements (for example, a back of a gate in a transistor) are exposed. Additional tiers may be added if desired essentially repeating this process.

First claim

What is claimed is:

1. A three dimensional (3D) integrated circuit (IC) (3DIC), comprising:
a first tier comprising:
a first holding substrate;
a first transistor positioned above the first holding substrate; and
a first interconnection metal layer positioned above the first transistor, wherein the first interconnection metal layer comprises a first metal bonding pad; and

a second tier comprising:
a second interconnection metal layer comprising a second metal bonding pad bonded to the first metal bonding pad;
a second transistor positioned above the second interconnection metal layer, the second transistor comprising a second gate and a second gate back surface; and
a second back gate bias positioned above and proximate the second gate back surface.

2. The 3DIC of claim 1 , further comprising a second back metal layer positioned above the second back gate bias.

3. The 3DIC of claim 2 , further comprising a via coupling the second back metal layer to the second interconnection metal layer.

4. The 3DIC of claim 2 , wherein the second back metal layer comprises a second back metal bonding pad.

5. The 3DIC of claim 1 , wherein the first holding substrate comprises a silicon holding substrate.

6. The 3DIC of claim 1 , wherein the first holding substrate comprises a glass holding substrate.

7. The 3DIC of claim 1 , further comprising a first back gate bias positioned proximate a gate of the first transistor.

8. A three dimensional (3D) integrated circuit (IC) (3DIC) comprising:
a first tier comprising:
a first holding substrate;
a first interconnection metal layer positioned above the first holding substrate;
a first transistor positioned above the first interconnection metal layer;
a first metal back layer positioned above the first transistor, wherein the first metal back layer comprises a first metal bonding pad; and
a via coupling the first metal back layer to the first interconnection metal layer; and

a second tier comprising:
a second interconnection metal layer comprising a second metal bonding pad bonded to the first metal bonding pad;
a second transistor positioned above the second interconnection metal layer, the second transistor comprising a second gate and a second gate back surface; and
a second back gate bias positioned above and proximate the second gate back surface.

9. The 3DIC of claim 8 , further comprising a second back metal layer positioned above the second back gate bias.

10. The 3DIC of claim 9 , further comprising a via coupling the second back metal layer to the second interconnection metal layer.

11. The 3DIC of claim 9 , wherein the second back metal layer comprises a second back metal bonding pad.

12. The 3DIC of claim 8 , further comprising a first back gate bias positioned proximate a gate of the first transistor.

13. The 3DIC of claim 1 integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a mobile phone; a cellular phone; a computer; a portable computer; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; and a portable digital video player.

14. The 3DIC of claim 8 integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a mobile phone; a cellular phone; a computer; a portable computer; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; and a portable digital video player.

Assignees

• Qualcomm Inc

Inventors

• Du Yang
• Arabi Karim

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W90/792

  between multiple chips · CPC title

• H10W90/20

  Configurations of stacked chips · CPC title

• H10W80/327

  characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers · CPC title

• H10W80/312

  characterised by the direct bonding of electrically conductive pads · CPC title