Molybdenum deposition

US12074029B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12074029-B2
Application numberUS-202217814209-A
CountryUS
Kind codeB2
Filing dateJul 21, 2022
Priority dateNov 19, 2018
Publication dateAug 27, 2024
Grant dateAug 27, 2024

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Provided herein are low resistance metallization stack structures for logic and memory applications and related methods of fabrication. The methods involve forming bulk conductive films on thin low resistivity transition metal layers that have large grain size. The bulk conductive films follow the grains of the low resistivity transition metal films, resulting in large grain size. Also provided are devices including template layers and bulk films.

First claim

Opening claim text (preview).

The invention claimed is: 1. A method comprising: forming a first molybdenum (Mo) layer by exposing a substrate in a reaction chamber to a molybdenum oxychloride and boron-containing reducing; and forming a bulk conductive layer on the first Mo layer using hydrogen (H 2 ) as a reducing agent wherein the bulk conductive layer is formed by ALD. 2. The method of claim 1 , wherein the bulk conductive layer is a molybdenum (Mo) layer. 3. The method of claim 1 , wherein forming the first Mo layer further comprises exposing the substrate to H 2 . 4. The method of claim 1 , wherein the substrate temperature during formation of the first Mo layer is between 300° C. and 800° C. 5. The method of claim 1 , wherein the molybdenum oxychloride is molybdenum dichloride dioxide (MoO 2 Cl 2 ). 6. The method of claim 1 , wherein the first Mo layer is formed by atomic layer deposition (ALD). 7. The method of claim 1 , wherein the bulk conductive layer is tungsten. 8. The method of claim 1 , wherein the first Mo layer has less than 1 (atomic) % impurities. 9. The method of claim 1 , wherein the first Mo layer is between 1 and 10 nm thick. 10. The method of claim 1 , wherein the first Mo layer overlies a dielectric layer. 11. The method of claim 1 , wherein the first Mo layer is free of fluorine impurities.

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Inventors

Classifications

  • the principal metal being a refractory metal · CPC title

  • for deposition from the gaseous phase, e.g. for chemical vapour deposition [CVD] · CPC title

  • by thermal treatment thereof · CPC title

  • H10P14/418Primary

    the conductive layers comprising transition metals · CPC title

  • H10W20/425Primary

    Barrier, adhesion or liner layers · CPC title

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What does patent US12074029B2 cover?
Provided herein are low resistance metallization stack structures for logic and memory applications and related methods of fabrication. The methods involve forming bulk conductive films on thin low resistivity transition metal layers that have large grain size. The bulk conductive films follow the grains of the low resistivity transition metal films, resulting in large grain size. Also provided…
Who is the assignee on this patent?
Lam Res Corp
What technology area does this patent fall under?
Primary CPC classification H10P14/418. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 27 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).