Small size pixel and display device including the same

Patent metadata

Field	Value
Publication number	US-12073773-B2
Application number	US-202117520890-A
Country	US
Kind code	B2
Filing date	Nov 8, 2021
Priority date	Apr 19, 2021
Publication date	Aug 27, 2024
Grant date	Aug 27, 2024

Abstract

A device includes a pixel array, a row driver configured to, generate a plurality of control signals, drive a plurality of rows of the pixel array using the plurality of control signals, and generate a plurality of clock signals, a row multiplexer configured to receive the plurality of clock signals, and transmit one clock signal of the plurality of clock signals, a data driver configured to transmit a plurality of data signals to the pixel array by column units, each pixel of the plurality of pixels includes, a light emitting device, a shift register configured to receive the selectively transmitted clock signal from the row multiplexer, and generate a width adjusted pulse width modulation (PWM) signal based on a desired brightness level of the light emitting device, and a transistor configured to transmit a driving current to the light emitting device based on the PWM signal.

First claim

What is claimed is:

1. A device comprising:
a pixel array including a plurality of rows, and each row of the plurality of rows includes a plurality of pixels;
a row driver configured to,
generate a plurality of control signals,
drive the plurality of rows of the pixel array using the plurality of control signals, and
generate a plurality of clock signals;

a row multiplexer configured to receive the plurality of clock signals, and selectively transmit one clock signal of the plurality of clock signals to the pixel array;
a data driver configured to transmit a plurality of data signals to the pixel array by column units; and
each pixel of the plurality of pixels includes,
a light emitting device,
a shift register configured to receive the selectively transmitted clock signal from the row multiplexer, and generate a width adjusted pulse width modulation (PWM) signal based on a desired brightness level of the light emitting device, and
a transistor configured to transmit a driving current to the light emitting device based on the PWM signal.

2. The device of claim 1 , wherein
the row driver is further configured to,
generate a data clock signal and a PWM clock signal, the data clock signal and the PWM clock signal included in the plurality of clock signals; and

the shift register is further configured to,
store the plurality of data signals during a data write period based on the data clock signal, and
output the PWM signal from during a light emission period based on a width adjustment of the PWM clock signal.

3. The device of claim 1 , wherein the plurality of pixels included in each row of the plurality of rows are configured to share a common row multiplexer.

4. The device of claim 1 , wherein
the row driver is configured to drive the plurality of rows during a frame period, the frame period including a data write period and a light emission period; and
the shift register includes a plurality of flip-flops, wherein each of the plurality of flip-flops is numbered 1 to N, where N is an integer greater than 1.

5. The device of claim 4 , wherein
the light emission period includes a plurality of subframe periods, each subframe period of the plurality of subframe periods having different durations; and
the row driver is further configured to toggle a PWM clock signal every subframe period based on a desired light emission time of the light emitting device.

6. The device of claim 5 , wherein
a number of subframe periods of the plurality of subframe periods is the same as a number of the flip-flops included in the shift register;
a duration for each subframe period of the plurality of subframe is equal to a duration of the light emission period divided by 2; and
n is incremented by 1 from 1 to N.

7. The device of claim 4 , wherein each pixel of the plurality of pixels further includes:
a write multiplexer configured to select a data signal of the plurality of data signals or a bit value stored in a desired flip-flop of the plurality of flip-flops, and output the selected data signal or the bit value to the shift register, wherein the desired flip-flop configured to store the PWM signal.

8. The device of claim 1 , wherein
each pixel of the plurality of pixels is further configured to be driven during a frame period, the frame period including a data write period and a light emission period; and
the shift register includes a plurality of latches, wherein each of the plurality of latches is numbered 1 to N.

9. The device of claim 8 , wherein
the row multiplexer includes a plurality of multiplexers corresponding to the plurality of latches; and
the plurality of multiplexers are configured to select one clock signal of the plurality of clock signals, and transmit the selected clock signal to the plurality of latches corresponding thereto.

10. The device of claim 8 , wherein
the shift register further includes a feedback latch, the feedback latch configured to store a bit value stored in a desired latch of the plurality of latches, the desired latch configured to output the PWM signal; and
each pixel of the plurality of pixels further includes a write multiplexer, the write multiplexer configured to select a data signal of the plurality of data signals or the bit value stored in the feedback latch, and output the selected data or the bit value to the shift register.

11. The device of claim 8 , wherein
the light emission period includes a plurality of subframe periods, each subframe period having different durations; and
the row driver is further configured to serially toggle a PWM clock signal every subframe period of the plurality of subframe period, and control a light emission time of the light emitting device based on the PWM clock signal.

12. The device of claim 11 , wherein
the row driver is further configured to toggle a feedback PWM clock signal every subframe period of the plurality of subframe periods, and toggle the feedback PWM clock signal before serially toggling the PWM clock signal.

13. The device of claim 1 , wherein the shift register is configured to store a plurality of bit values.

14. A device comprising:
a pixel array including a plurality of pixels, the plurality of pixels arranged in a plurality of rows and a plurality of columns, each pixel of the plurality of pixels including a light emitting device and a storage element;
a row driver configured to generate a plurality of control signals and a plurality of clock signals, and drive the pixel array by row using the plurality of controls signals and the plurality of clock signals including a first clock signal,
the row driver further configured to adjust a width of the first clock signal to control brightness of at least one light emitting device of the plurality of light emitting devices, and
the row driver is further configured to drive each pixel of the plurality of pixels during a frame period, the frame period including a plurality of subframe periods, and toggle the first clock signal once every subframe period of the plurality of subframe periods; and

a data driver configured to output a plurality of data signals to the pixel array by column.

15. The device of claim 14 , wherein
each subframe period of the plurality of subframe periods has a duration equal to a period of the frame divided by 2 n , where n is an integer incremented by 1 for each subframe period.

16. The device of claim 14 , wherein
the storage element is any one of a latch, a flip-flop, or a static random access memory (SRAM) configured to store a bit value; and
each pixel of the plurality of pixels includes,
a level shifter configured to receive at least one signal output by the storage element, and convert the received at least one signal into a corresponding voltage level, and
a first transistor configured to control turn ON or turn OFF the light emitting device of the pixel based on an output from the level shifter.

17. The device of claim 16 , wherein
the at least one signal output from the storage element includes a first signal and a second signal, the second signal complementary to the first signal; and
the level shifter includes,
an N-type transistor configured to receive the first signal; and
a P-type transistor configured to receive the second signal, and
the N-type transistor and the P-type transistor are each configured to receive a low level source voltage at a first end, respectively, and receive a high level source voltage at a second end, respectively.

18. The device of claim 14 , wherein the storage element includes:
a

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kwon Taehyeon
• Kwon Yongil
• Kang Sugyeung
• Kim Kangjoo
• Kim Sunkwon
• Park Hyunsang
• Lee Yilho

Classifications

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G2310/0289

  Details of voltage level shifters arranged for use in a driving circuit · CPC title

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title