Pulse-width-modulation control of micro LED

Patent metadata

Field	Value
Publication number	US-10720098-B2
Application number	US-201715814341-A
Country	US
Kind code	B2
Filing date	Nov 15, 2017
Priority date	Nov 15, 2017
Publication date	Jul 21, 2020
Grant date	Jul 21, 2020

Abstract

Embodiments relate to a micro light-emitting-diode (mLED) cell that includes a mLED and a controller. The controller receives a brightness data signal and generates a driving signal corresponding to the brightness data signal. The controller is coupled to the mLED for providing the driving signal that turns on the mLED for first times and turns off the mLED for second times for a duration of a cycle. The driving signal causes a current density in mLED to be above a threshold value when the mLED is turned on.

First claim

What is claimed is:

1. A micro-light-emitting-diode (mLED) display device comprising:
an mLED configured to emit light;
a controller receiving a brightness data signal and generating a driving signal corresponding to the brightness data signal, the controller coupled to the mLED for providing the driving signal that turns on the mLED for first times and turns off the mLED for second times for a duration of a cycle; and
a current source coupled between an output of the controller and the mLED to generate a driving current based on the driving signal, the driving current causing a current density in the mLED to be above a threshold value of 1 A/cm 2 when the mLED is turned on.

2. The mLED display device of claim 1 , wherein the current source comprises a transistor that is configured to turned on and off based on the output of the controller.

3. The mLED display device of claim 1 , wherein the controller comprises:
a memory including a plurality of memory cells, the memory further including a plurality of memory outputs, each memory output corresponding to an output of a memory cell, the memory storing the brightness data signal; and
a plurality of gates, each gate of the plurality of gates comprising:
a first input node coupled to a memory output of the plurality of memory outputs,
a second input node coupled to a periodic pulse signal of a plurality of periodic pulse signals, and
an output node, the output node configured to output a signal having a high level when the memory output and the periodic pulse signal have a level higher than a threshold value, and output a signal having a low level when the memory output or the periodic pulse signal have a level lower than the threshold value.

4. The mLED display device of claim 3 , wherein a number of memory cells of the memory is equal to a bit depth of the brightness data signal.

5. The mLED display device of claim 3 , wherein the controller further comprises:
a second memory including a plurality of memory cells, the second memory cell further including a plurality second of memory outputs, each output of the plurality of second memory outputs corresponding to an output of a second memory cell; and
a plurality of multiplexers; each multiplexer of the plurality of multiplexers coupled to a memory output and a second memory output;
wherein each of the plurality of gates is coupled to a multiplexer of the plurality of multiplexers.

6. The mLED display device of claim 5 , wherein:
the first memory is enabled for writing when the plurality of multiplexers are configured to select the output of the second memory, and
the second memory is enabled for writing when the plurality of multiplexers are configured to select the output of the memory.

7. The mLED display device of claim 3 wherein the plurality of gates comprises:
a first gate coupled to a first output of the memory and a first periodic pulse signal; and
a second gate coupled to a second output of the memory and a second periodic pulse signal;
wherein the second periodic pulse signal has a pulse duration that is twice as long as a pulse duration of the first periodic pulse signal.

8. The mLED display device of claim 7 , wherein a pulse of the second periodic pulse signal starts after an end of a pulse of the first periodic pulse signal.

9. The mLED display device of claim 7 , wherein a pulse width of the first periodic pulse signal is inversely proportional to a refresh rate of the mLED cell and a bit-depth of the brightness data signal.

10. The mLED display device of claim of claim 7 , further comprising:
a third AND gate coupled to a third output of the memory and a third periodic pulse signal,
wherein the third periodic pulse signal has a pulse duration that is twice as long as the pulse duration of the second pulse signal.

11. A micro-light-emitting-diode (mLED) driver circuit comprising:
a memory including a plurality of memory cells, the memory further including a plurality of memory outputs, each memory output corresponding to an output of a memory cell, the memory storing a value of a brightness data signal; and
a plurality of gates, each gate of the plurality of comprising:
a first input node coupled to a memory output of the plurality of memory outputs,
a second input node coupled to a periodic pulse signal of a plurality of periodic pulse signals, and
an output node, the output node configured to output a signal having a high level when the memory output and the periodic pulse signal have a level larger than a threshold value, and output a signal having a low level when the memory output or the periodic pulse signal have a level smaller than the threshold value; and

a current source, the current source coupled to an output of each of the gates, the current source generating a driving current within a frame based on the outputs of each of the gates, an average amplitude of the driving current based on the brightness data value, the driving current causing a current density in an mLED to be above a current density threshold value of 1 A/cm′ when the mLED is turned on.

12. The mLED driver circuit of claim 11 , further comprising:
a second memory including a plurality of memory cells, the second memory cell further including a plurality second of memory outputs, each output of the plurality of second memory outputs corresponding to an output of a second memory cell; and
a plurality of multiplexers; each multiplexer of the plurality of multiplexers coupled to a memory output and a second memory output;
wherein each of the plurality of gates is coupled to a multiplexer of the plurality of multiplexers.

13. The mLED driver circuit of claim 11 wherein the plurality of gates comprises:
a first gate coupled to a first output of the memory and a first periodic pulse signal; and
a second gate coupled to a second output of the memory and a second periodic pulse signal;
wherein the second periodic pulse signal has a pulse duration that is twice as long as a pulse duration of the first periodic pulse signal.

14. The mLED driver circuit of claim 13 , wherein a pulse of the second periodic pulse signal starts after an end of a pulse of the first periodic pulse signal.

15. The mLED driver circuit of claim 13 , wherein a pulse width of the first periodic pulse signal is inversely proportional to a refresh rate of the mLED driver circuit and a bit-depth of the brightness data signal.

16. A method for operating a micro-light-emitting-diode (mLED), comprising:
generating a driving signal corresponding to a brightness data signal;
generating, by a current source, a driving current based on the driving signal;
turning on the mLED for first times in a duration of a cycle by the driving current to cause a current density in mLED to be above a threshold value of 1 A/cm 2 ; and
turning off the mLED for second times in the duration of the cycle by the driving current.

17. The method of claim 16 , wherein generating the driving signal comprises:
storing the brightness data value in a memory cell of an mLED cell, the brightness data value indicative of a desired brightness for the mLED;
receiving multiple periodic pulse signals, the multiple periodic pulse signals including:
a first periodic pulse signal, and
a second periodic pulse signal, the second pulse signal having a pulse width that is double a pulse width of the first periodic pulse signal;

generating a digital pulse-width-modulation (PWM) signal by ANDing each bit of the brightness data value with a pulse signal of the multiple periodic pulse signals;
generating a driving sig

Assignees

• Facebook Tech Llc

Inventors

• Valentine Gareth John

Classifications

• G09G3/2014 Primary

  by modulation of the duration of a single pulse during which the logic level remains constant · CPC title

• G09G2300/08

  Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements · CPC title

• G09G3/3241

  the current through the light-emitting element being set using a data current provided by the data driver, e.g. by using a two-transistor current mirror · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G3/2088

  with use of a plurality of processors, each processor controlling a number of individual elements of the matrix · CPC title